VHDL newbie : package and "use" directive

Altera_Forum · ‎03-11-2011

Hi !

However hard I try to insert those 2 lines in my vhdl top level design (multiplexer.vhd) :

library WORK;

use WORK.multiplexer_Pkg.all;

my component instantiations located in my top level design source file need a full context to be compiled !

May I as you some hints ?

Attached my 3 sources.

Cheers !

Sylvain

Altera_Forum · ‎03-11-2011

Theres no problem with this code. It compiles for me.

Altera_Forum · ‎03-11-2011

Hi Tricky !

Thanks for your answer.

If you replace the line 68 of multiplexer.vhd :

genericMultiplexer_i :  work.genericMultiplexer( genericMultiplexerArchi )

by

genericMultiplexer_i :  genericMultiplexer( genericMultiplexerArchi )

it won't compile whereas it should, at least if I've got a grip with "use package" statement ... :-(

Cheers !

Sylvain

Altera_Forum · ‎03-11-2011

Hi,

package is for procedures and functions. (not 100% sure)

If you want to instantiate "genericMultiplexer" (written in genericMultiplexer.vhd),

You have to write in architecture of your "multiplxer.vhd" something like


genericMultiplexer_i :  ENTITY work.genericMultiplexer( genericMultiplexerArchi )
generic map ( selectorWidth => mySelectorWidth ) -- mySelectorWidth ?
port map ( 
  selector  => selector,
  dataInput => dataInput,
  output    => output 
);

It is enough.

Your package body is empty, and your package is useless. (In my opinion)

Altera_Forum · ‎03-11-2011

--- Quote Start ---

Hi,

package is for procedures and functions. (not 100% sure)

--- Quote End ---

You can put component declarations in a package, but its a habit formed a long long time ago before direct isntantiation was brought into the language (1993) and supported by the tools.

Component declarations are messy because you have to maintain essentially two copies of the same thing, and its too easy to update the entity and forget to update the component.

But It can be useful to have a package without a body. A setup package containing types and constants for example.

Altera_Forum · ‎03-11-2011

Dear mmTsuchi, dear Tricky,

Thanks for your replies.

Dear mmTsuchi, I knew about direct entity instanciation you pointed out.

My point was to try to use component instanciation along with a package "use" clause for two reasons :

1) By declaring components in a package and by maintaining their architecture in the package body, I thought it might be a good way to avoid the 2 copies maintenance which Tricky was talking about.

2) By adding "use myPackage" clause at the beginning of a new design unit implementation file, it may lighten the code by removing selected names convention and by removing the component port declarations before its instantiation.

Eventually, it looks like the most efficient way to deal with instantiations, is to use "entity instantiation" (which was mentioned by mmTsuchi) rather than my "component instantiation" along with a package use clause, and to keep packages only for constants or types declaration.

I'am an absolute beginner and I try to catch some good habits right from the start.

Your advices are very welcome !

Cheers !

sylvain

Altera_Forum · ‎03-17-2011

forum coding guidelines for vhdl and verilog hdl (http://www.alteraforum.com/forum/showpost.php?p=3368&postcount=1)