VREFB pin in Cyclone V

[HiOh]

I am checking the pin connections for Cyclone V (5CGXFC7D6F27I7N).

I want to confirm if it is okay to leave VREFB3AN0 open, but there is no mention of it in the Pin Connection Guidelines (PCG-01014-3.2). (There is a mention of VREF[#]N0.) All IOs used in the 3A bank are 3.3V CMOS.

Is it okay to leave it open?

If not, what kind of issues might arise?

Thank you for your help.

[FvM]

Hi,
VREF pins are only used for voltage referenced I/O-standards HSTL and SSTL. IMHO you can leave it open if you enable weak pull-up for unused pins.

VREF[#]N0 means all VREF pins. Pin connection guidelines are suggesting "If the VREF pins are not used, you should connect them to either the VCCIO in the bank in which the pin resides or GND".

[HiOh]

Thank you for your prompt response.

To add a weak pull-up to the VREF pins, I should set "As input tri-stated with weak pull-up" in Device and Pin Options -> Unused Pins, correct? I didn't realize that VREF pins could be set as unused pins.

Although there is no mention of a pull-up for "VREFB3AN0" in the *.pin file, considering that other unused user I/O pins are set to "RESERVED_INPUT_WITH_WEAK_PULLUP," can I assume that the VREFB3AN0 pin is also pulled up?

[FvM]

Hi,

you are right VREF pin of Cyclone V is dedicated pin without IO function, other Cyclone families have shared  VREF and IO. Thus Cyclone V VREF hasn't pull-up feature and should be connected to GND or VCCIO when unused. 

Sorry for causing confusion.

Regards
Frank

[HiOh]

Thank you very much.

The reason I asked this question in the first place is that multiple boards have faulty JTAG pins (Bank3A), and I was trying to find the cause. 

Is it possible for such a situation to occur if the VREFB3AN0 pin is used as an open? 

Regards

[AqidAyman_Intel · Accepted solution]

Hello,

Since it is mentioned in the Pin Connection Guideline that the pin needs to connect either GND or VCCIO if not used, then I am afraid you can't leave it floating.

Although I can't confirm with you that this is the cause of those faulty JTAG pins, I guess what will happen to the pin if left floating is the output of the buffer logic will be undefined since those pins are voltage-reference pins. It means that the pin should be connected to a valid logic for the hardware to work as expected.

[HiOh]

I appreciate your response. I understand that it is indeed difficult to accurately determine the consequences of performing actions that are not recommended. First, I will address the floating state of the input pins. Thank you for your advice.

[FvM]

Hi,
I wonder what "faulty JTAG pins" actually means? Does it mean JTAG doesn't work at all, or just seeing unreliable operation?
I experienced some cases where JTAG signals, specifically TCK, suffered from crosstalk of other signals on the board. Problem is relative large driver impedance of some JTAG adapters, e.g. classical USB Blaster which can lead to bad JTAG signal quality.

I won't expect actual problems from floating VREF pins, but I have it connected to GND in all Cyclone V designs, so it's only an educated guess.

Regards
Frank

[HiOh]

Sorry for the delayed response.

"Faulty JTAG pins" refers to physical faults. Specifically, the symptoms are as follows: TDI-N5 5.3Ω (short), P3.3-TCK 5.2Ω (short), TCK-N5 376Ω (short), P3.3-TDI 8.2Ω (short), TDO-N5 1.8Ω (short).

I suspected a potential difference between the GND of the JTAG cable and the GND of the board, or ESD, but I have not been able to identify the cause so far. Therefore, I wanted to confirm whether the open VREF could be the cause.

Regards