Verilog Generic Input ports

[Altera_Forum]

Hi All, 

 I have an input port to a module which is 5 bits say Inp_A[4:0]. Now the number of such inputs depends on a generic parameter say Gen_Nm.  How can i declare such an input ports in my module. I have tried Input [4:0][Gen_Num-1 : 0] Inp_A; & Input [Gen_Num-1 : 0][4:0] Inp_A; & Input [Gen_Num-1 : 0] Inp_A[4:0]; & Input [4:0] Inp_A[Gen_Num-1 : 0];  All these seems to be giving compile error.  Please help me, how to go about this  regards, freak

[Altera_Forum]

your last example is the correct one. 

check that parameter is declared within the same file like :  module dummy_mod( Inp_A ); parameter Gen_Num = 3 input [4:0] Inp_A [Gen_Num-1:0]; // should give Gen_Num x 5 bit input endmodule  but i have seen that quartus sometimes seems to have problems with parameters if i use them then i do the following  parameter ReloadValue = 47;  wire [5:0] wReloadValue; assign wReloadValue = ReloadValue;  somewhere this can be used as rTestReg <= rMyValue + wReloadValue ;  assigning a wire with the parameter works, using the parameter directly doesn't no idea why

[Altera_Forum]

Hi Schmitt, 

  The example given  input [4:0] Inp_A [Gen_Num-1:0]; // should give Gen_Num x 5 bit input is not working.   The compiler is throwing error saying that, this is a System Verilog construct. Verilog does not support Memory type port declaration.   What is your thoughts on this .  regards, freak