Verilog to VHDL

Altera_Forum · ‎11-22-2007

Can some one tell my what this code is in VHDL?


  always @(posedge vga_clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sync_n <= 0;
      else if (1)
          sync_n <= vga_start ? (vsync_temp ~^ hsync_temp) : sync_n_init;
    end

Some think like this?


  process (vga_clk, reset_n)
  begin
    if reset_n = '0' then
      sync_n <= std_logic'('0');
    elsif vga_clk'event and vga_clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        sync_n <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(vga_start) = '1'), (vsync_temp xnor hsync_temp), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(sync_n_init)))));
      end if;
    end if;

Only (vsync_temp xnor hsync_temp) is wrong I think.

Altera_Forum · ‎11-26-2007

The operator ~^ is a XNOR.

vsync_temp ~^ hsync_temp

0 ~^ 0 is 1

0 ~^ 1 is 0

1 ~^ 0 is 0

1 ~^ 1 is 1

depending on vga_start,

if 1 sync_n is set to the result of the xnor ,

if 0 sync_n is set to the value of sync_n_init;

unfortunately i cannot read VHDL, it's too much to type, thats why i do it with verilog

Altera_Forum · ‎11-26-2007

I believe the following example would be equivalent VHDL for your Verilog. The

VHDL you provided appears to be machine generated.

process (reset_n, vga_clk)

begin

if (reset_n = '0') then

sync_n <= '0';

elsif (vga_clk'EVENT and vga_clk = '1') then

if (vga_start = '1') then

sync_n <= vsync_temp xnor hsync_temp;

else

sync_n <= sync_n_init;

end if;

end process;