Very simple question, first time using Verilog here...

[Altera_Forum]

Hello all... 

  My name is Craig and this is my first post. I just started taking a course in HDL using Verilog. I've been beating my head against the wall for days over a very simple problem I'm having programming with Verilog using the ModelSim software from Altera.     My code is below. It's just a parity-bit generator. It takes 7 bits from a bus and puts out (is supposed to) a parity bit. It all works flawlessly, except for one major problem in which the "odd_number_of_ones" variable never gets changed. I KNOW that's the problem cause I've troubleshooted every other possible problem. Whenever I simulate the code using a testbench, I just get out a constant '0', no matter what combination I put in for the input (parityresult[7] is always 0). Help! Thanks is advance!   CODE:   // 7-bit parity bit generator // obj_7bit_paritybitgenerator.v // Craig Chaney // January 29, 2009 // This code takes in 7 bits from a bus and outputs the // original 7 bits and an extra parity bit for a total // of 8 bits. `timescale 100 ns / 10 ns module obj_7bit_paritybitgenerator(bus_bits, parityresult);  //Define the inputs/outputs for the circuit.  input [6:0] bus_bits;  output [7:0] parityresult;  wire [7:0] parityresult;    //Declare a 1-bit register which holds the new potential  //value for the parity bit.   reg odd_number_of_ones;     //Initialize the module by clearing the odd_number_of_ones  //register, indicating that the new parity bit should be  //a '0' by default.  initial  begin  odd_number_of_ones = 1'b0;  end    //Loop through all 7 bits on the input bus and   //assign them to 7 of the 8 bits on the output without  //being changed. Also, check to see if any one of the bits  //is a '1'. If so, toggle the value of the parity bit.  integer k;  initial   begin  odd_number_of_ones = 1'b0;  for(k=0;k<=6;k=k+1)  if(bus_bits[k]==1)  begin  odd_number_of_ones = ~odd_number_of_ones;  end  //end  end    //Assign the parity bit determined by the above logic to  //the output bus.  assign parityresult[7] = odd_number_of_ones; endmodule

[Altera_Forum]

I hope you don't expect this code to be systhesizable into an FPGA or whatever. It is not. Concerning the logical function please note that the relevant code lines are inside an initial statement and, thus, will only be executed once. Use a statement that triggers these lines every time an input signal changes.

[Altera_Forum]

Harald is right, you should do something like 

 `timescale 100 ns / 10 ns module obj_7bit_paritybitgenerator ( bus_bits, parityresult );  //Define the inputs/outputs for the circuit. input [6:0] bus_bits; output [7:0] parityresult; wire [7:0] parityresult;  // maybe your parity bit must be inverted. assign parityresult[7] = bus_bits[0] ^ bus_bits[1] ^ bus_bits[2] ^ bus_bits[3] ^ bus_bits[4] ^ bus_bits[5] ^ bus_bits[6];  // question what about the parityresult[6:0] ???  endmodule  But be aware that your parity is a wire and therefore could have some glitches. the next module should synchronize it to a clock. so always use full synchronous design whenever possible  // always @ ( posedge clk ) // begin // insert your code here ... // end  regards   michael