Our company requires a developer for a project who has the following experience:
- Altera Quartus Verilog development
- Experience with Altera ALTGX / ALTGX_RECONFIG cores
- Stratix 4 transceiver experience is good
- Experience running multiple protocols in a transceiver bank
Please see:
Configuring Multiple Protocols and Data Rates in Stratix IV Devices:
google: stx4_siv52003
- Experience digging into unfamiliar Verilog in order to merge projects.
- Experience fishing out and 'bubbling-up' signals to higher levels in
order to route to new modules.
- Many years of expertise in solving Verilog/RTL issues
This project is related to low latency financial trading, and may
lead to other projects.
Please contact our company via private msg, or directly:
quartus.verilog.developer@gmail.com
