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Warning: (vsim-3473)

Altera_Forum
Honored Contributor I
1,256 Views

Hi dear all, 

Can somebody help me? I have little question. The folowing net list compiles without error but simulation gives worning. Plise help me!!! 

 

--********************************************************* 

library ieee; 

use ieee.std_logic_1164.all; 

entity basic is 

port(input : in bit; 

output: out bit); 

end basic; 

architecture B1 of basic is 

begin 

output <= not input; 

end B1; 

--********************************************************* 

--********************************************************* 

library ieee; 

use ieee.std_logic_1164.all; 

entity second is end second; 

architecture B2 of second is 

component lebel is 

port (in_1 : in bit; out_1 : out bit); 

end component; 

signal in_1, out_1 :bit; 

begin 

a1: lebel port map(in_1, out_1); 

end B2; 

--********************************************************* 

--********************************************************* 

library ieee; 

use ieee.std_logic_1164.all; 

configuration config of second is 

for B2 

for a1: lebel 

use entity work.basic(B1) 

port map (in_1, out_1); 

end for; 

end for; 

end config; 

--********************************************************* 

--********************************************************* 

that is the Worning message-** Warning: (vsim-3473) Component instance "a1 : lebel" is not bound.
0 Kudos
3 Replies
Altera_Forum
Honored Contributor I
223 Views

you havent included the source code for the lebel entity

Altera_Forum
Honored Contributor I
223 Views

sorry but can you more detaily write how can it i do?

r_m_n
Beginner
196 Views

Hey,

Have you solved this? I am running into an identical problem and I don't know how to fix this.

Cheers!

Reply