Hi,
I am working on specifying a new system and selecting devices.
So far the Cyclone V GT devices look good for one of those devices.
But I am trying to resolve the performance potential of the Serdes transceivers and PHY (PCS+PMA).
The transceivers are speced at 6.144 Gb/sec in the device catalog.
But in this document I see all supported protocols listed as well below that:
http://www.altera.com/technology/high_speed/protocols/all-protocols/ip/hs-ip-protocol-data-rates.html Also in this document on the Cylone V Transceiver architecture I see a specific reference :"You can configure Cyclone V GT devices to support 6.144 Gbps for CPRI protocol only."
http://www.altera.com/literature/hb/cyclone-v/cv_53001.pdf Are these limitations just because of the Altera supplied controllers?
With custom designed or 3rd party controllers which use 32 or 40 bit double wide interfaces to the PCS is it possible to utilize the full 6.144 capabilities of the transceivers?
Also in a similar question I see references in the Cyclone V custom transceiver configurations document:
http://www.altera.com/literature/hb/cyclone-v/cv_53005.pdf to up to 5 Gb/sec data rate for a 'double wide' interface to the PCS from the FPGA fabric. That seems to suggest that the limitation for the specific protocols is because of the controllers!? I assume the 5Gb/sec is the overall available data rate at the FPGA core interface including 8b/10b overhead using A 6.144 Gb/sec 'wire-speed'.
I would like to understand the nature of the limitations to help design our system and select appropriate devices.
Thanks Martin
