What can I do to 'hint' the optimizer??

Altera_Forum · ‎03-22-2013

A while back we had a soft reset signal generated from the result of a write to a register block from a processor. This signal would then be brought to many other modules and used as resets/clears and would determine state transitions and such, if set.

The register block has since been depracated, and we hard tie this soft reset signal to '0' in code. Because it's tied to 0, I would imagine that all of the logic in other modules that check for the signal to be asserted should instead be optimized away.

But when I go into timequest, I can see the paths are still valid. Is there any way to hint to the tools that this is no longer a valid path and to please optimize it away? I'd prefer not to remove all of the instances of the signal, because I don't know about its impact in other projects.

Altera_Forum · ‎03-24-2013

You should not have to do nothing else.

Where do the leftover paths start?

Altera_Forum · ‎03-25-2013

Here is what is essentially my code... theres a bunch missing but this is the critical path:

in module A:

assign reset_out = 1'b0;

in module B:

assign c_reset = reset_out

always @(posedge clock or negedge reset_n)

if (!reset_n)

c_state <= IDLE;

else if (c_reset)

c_state <= RESET;

else

c_state <= n_state;

from there, we do a d_state (delayed state) of c_state and do:

assign phy_reset = (c_state == RESET) && (d_state != RESET);

then fan out phy_reset to a bunch of FFs for synchronous clears. The problem comes where I would hope the state machine optimizer would reduce the states and ignore the RESET state. If I go into timequest, I can run a timing report through phy_reset and come up with valid paths

Altera_Forum · ‎03-25-2013

So I suspect my issue is with my state machine not being recognized as a valid state machine, and thus not being optimized. Oh well. Thanks folks