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Altera_Forum
Honored Contributor I
699 Views

What do timing constraints really do

Hi guys, I am a little confused about timing constraints. 

 

Does timing constraints really change how the signals perform or it describes how the signals really look like for timing analysis? 

 

For example, if I have an external 100MHz clock input. It's 5.1 ns high and 4.9 ns low, but I want a 50% high and 50% low. 

 

How should I do the timing constraint?  

 

"create_clock -name {clk_100M} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk_100M}]" 

or  

"create_clock -name {clk_100M} -period 10.000 -waveform { 0.000 5.100 } [get_ports {clk_100M}]"? 

 

Thanks! 

 

Leon
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4 Replies
Altera_Forum
Honored Contributor I
30 Views

The main use for timing constraints is to guide the Fitter to place and route the design to meet your timing requirements, so you have to accurately describe the properties of your clocks. You have to provide, at a minimum, constraints for all clocks and for all I/O in the design. The Fitter takes this information to make decisions about how to place and route the internal design. Timing analysis will show you what the Fitter may be able to achieve (if you look at a post-map netlist) and what it actually does achieve (if you look at a post-fit netlist). 

 

For the base clock constraint you've specified, it simply needs to be: 

 

create_clock -period 10.000 [get_ports {clk_100M}] 

 

-waveform is only needed if the clock is not 50% duty cycle (is your clock really high for 5.1 ns and low for 4.9 ns?) or if it is phase shifted with respect to another clock (usually used for source synchronous interfaces). -name is only needed if the name of the clock should be different from the targeted port. 

 

See this online training and its follow-on courses for details: 

 

https://www.altera.com/support/training/course/odsw1115.html
Altera_Forum
Honored Contributor I
30 Views

Timing constraints can change the design routing but not modify a clock duty cycle. They describe the actual properties of an external clock. Duty cycle specifications a only relevant if both clock edges are used as event in your design.

Altera_Forum
Honored Contributor I
30 Views

 

--- Quote Start ---  

The main use for timing constraints is to guide the Fitter to place and route the design to meet your timing requirements, so you have to accurately describe the properties of your clocks. You have to provide, at a minimum, constraints for all clocks and for all I/O in the design. The Fitter takes this information to make decisions about how to place and route the internal design. Timing analysis will show you what the Fitter may be able to achieve (if you look at a post-map netlist) and what it actually does achieve (if you look at a post-fit netlist). 

 

For the base clock constraint you've specified, it simply needs to be: 

 

create_clock -period 10.000 [get_ports {clk_100M}] 

 

-waveform is only needed if the clock is not 50% duty cycle (is your clock really high for 5.1 ns and low for 4.9 ns?) or if it is phase shifted with respect to another clock (usually used for source synchronous interfaces). -name is only needed if the name of the clock should be different from the targeted port. 

 

See this online training and its follow-on courses for details: 

 

https://www.altera.com/support/training/course/odsw1115.html 

--- Quote End ---  

 

 

Thank you so much sstrell!
Altera_Forum
Honored Contributor I
30 Views

 

--- Quote Start ---  

Timing constraints can change the design routing but not modify a clock duty cycle. They describe the actual properties of an external clock. Duty cycle specifications a only relevant if both clock edges are used as event in your design. 

--- Quote End ---  

 

 

Thank you so much FvM!
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