What does "charge pump" and "loop filter components" do in Altera PLL?

[Altera_Forum]

What is the application of the "charge pump" and "loop filter components" and why should we want to be able to control them?

[Altera_Forum]

Hi XAUI, 

 if you really want to go into detail, I recommend this book:http://www.ti.com/tool/pll_book (http://www.ti.com/tool/pll_book). Also, if you're using PLLs for clock data recovery, Wikibooks has a nice one: https://en.wikibooks.org/wiki/clock_and_data_recovery (https://en.wikibooks.org/wiki/clock_and_data_recovery).  Okay, I'm trying to answer your question in simple words in case you don't care about the details: the charge pump and the loop filter form a unit which determines how much or how fast the VCO is tuned if a phase mismatch is detected (i.e. the PLL runs too fast or too slow). In other words, the bandwidth of the PLL.  A high bandwidth means that the PLL output frequency follows frequency variations of the reference signal. A low bandwidth means that the output frequency can only follow slow reference input frequency changes, but ignores fast changes; it also means you PLL needs more time to lock. As you can see, the desired bandwidth depends on your specific requirements. It is often desired to have a low bandwidth, so that you get some sort of jitter cleaning, but in other applications might also be desired to have a high bandwidth so that the PLL tracks the reference frequency.  You can adjust the PLL bandwidth by adjusting the loop filter and the charge pump. In a typical PLL design, the loop filter is a fixed circuit, while the charge pump gain can be adjusted in a certain range. I don't know if some FPGAs allow to adjust the loop filter e.g. using capacitor banks, maybe that's what "Loop Filter Components" means.  The charge pump can also have some constant leakage current, which affects the phase of the generated clock signal. However, typically this is not pointed out as a charge pump parameter, but instead abstracted just as a "clock phase" setting.  I assume you were confronted with those terms when trying to configure a PLL for a certain standard, e.g. PCIe. Those standards typically define a reference PLL model, and it's recommended to follow that. For example PCIe might use SSC, which means your reference clock varies over time (0.5% deviation, modulated with 33 kHz). Your PLL's bandwidth must be large enough to track that deviation, otherwise you filter out that deviation, defeating its purpose.   Best regards, GooGooCluster