The Table 36 of the MAX10 datasheet presents the minimum and maximum "True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices".
I have the following questions about this information:
1. What is meant by "high-speed and low-speed I/O performance pins", what is special about these pins?
2. What is a "True PPDS and Emulated PPDS_E_3R Transmitter" and why do we need it?
3. What is meant by the "Mode" column in this and other tables?
And the most important question which is rather confusing,
4. Why do we have a minimum rate for the HSIODR and fHSCLK? Having a minimum Data rate for the high-speed I/O performance pin does not make sense to me.
1. The low speed I/O banks have lower maximum frequency than other I/O banks
because of longer propagation delays. However, the delays do not affect the timing
parameters such as slew rate, rise time, and fall time.
2. True PPDS have better timing performance due to that the p and n are delayed equally. Emulated PPDS are GPIO that are created to invert each other, and external termination resistor is required. For the termination scheme, See: https://www.intel.com/content/www/us/en/programmable/documentation/sam1394433606063.html#sam13944362...
3. Mode here means how many data lanes. x4 means 4 data lanes to 1 clock, x8 means 8 data lanes to 1 clock and so on
4. Each mode have a different range of data rate. Example x1 have min 10 and max 100...meaning you if you have 1 data lane implementation, you have the choice to transfer between 10~100Mbps. But if you have x10, your min and max is 1, meaning you have no choice but to each lane transfer at 10Mbps (to have an aggregated 100Mbps for all 10 lanes)