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Altera_Forum
Honored Contributor I
1,356 Views

What is the best way to generate multiple clocks with minimum jitter and delays?

Hi, 

 

I have to generate several clocks on Arria 10 SoC board. The clocks and their applications are as follows: 

  1. 3GHz clock: for clocking external ADC to sample the incoming data, and receive it at transceiver pins using JESD204B IP.  

  2. 1.5GHz clock: to transmit the data from transceiver pins using Transceiver PHY IP (PMA width = 10)  

  3. 150MHz clock: to clock the coreclock of Transceiver PHY for transmitting data at 1.5GHz  

 

 

I think I have two options: 1) instantiate several PLLs and 2) generate 3GHz clock using fPLL from the 50MHz reference clock and use counters to create lower-frequency clocks. The first option does not seem to be good as each PLL would have its own locking time and would be located at different places, which would add phase delays due to route lengths. For the second option, I am not sure how reliable the counter would be while running at 3GHz.  

 

Please suggest what would be the best way to generate the above-frequency clocks so that they have minimum phase delay and jitter? 

 

Thanks, 

Arvind
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7 Replies
Altera_Forum
Honored Contributor I
71 Views

Hey Arvind, 

 

You could use a fPLL to generate the 3GHz clock and 1.5GHz clocks. Then cascade another PLL with this one and generate the 150MHz clock. You could use them in the source-synchronous mode or the Zero-delay mode and have their reset's tied together. Yes, the PLLs in this case may have different locking periods but that can't be avoided. Using one PLL for generating higher frequencies and another for the lower frequencies would be a good option.
Altera_Forum
Honored Contributor I
71 Views

Hi,  

 

Thank you for replying. The 1.5GHz and 3GHz outputs from fPLL and zero-delay mode 150MHz output from a cascaded PLL would work for me. However, I think it's not possible to generate a 150MHz clock output using a PLL from 1.5GHz clock. I also checked it: the transceiver PLL's don't supports outputs below 800MHz, while the IOPLL cannot take reference clock frequency more than 700MHz.  

 

Another option is to first generate a clock at 150MHz using IOPLL in zero-delay mode, and then use it as a reference clock to generate 1.5GHz and 3GHz clocks using an fPLL. However, the fPLL does not show the option to source-synchronize the outputs.  

Please let me know if you have any suggestions. 

 

Thanks.
Altera_Forum
Honored Contributor I
71 Views

Where do you see an option to send external clock > 800 MHz from Arria 10?

Altera_Forum
Honored Contributor I
71 Views

No, there is no external clock here. I want to generate three synchronized clocks at frequencies 150MHz, 1.5GHz, and 3GHz; the first two would be used at the Arria 10 Transceiver PHY to send data at 3Gbps (1.5GHz), while the last one (3GHz) would be used to sample the received analog signal at external high-speed ADC. My question here is that how can I generate these three clocks such that they are synchronized. The synchronization is important to get the time of flight of the transmitted signal, which is essential for the application.  

 

Please let me know if you have any suggestions on how can I generate these clocks. I have tried several options (I have described them above) using the PLLs available for Arria 10 SoC, but they did not work for me.
Altera_Forum
Honored Contributor I
71 Views

 

--- Quote Start ---  

while the last one (3GHz) would be used to sample the received analog signal at external high-speed ADC 

--- Quote End ---  

 

Yes, that's my point. Where do you connect the ADC clock input?
Altera_Forum
Honored Contributor I
71 Views

I see. I was thinking of taking the output clock through the transceiver pins of the FMC connector. I think I'll have to use the clock on the ADC board for sampling then.  

However, the problem of synchronizing the 150MHz and 1.5GHz still remains.
Altera_Forum
Honored Contributor I
71 Views

Generating a clock signal on transceiver pins might be possible under circumstances by sending a constant 01010101 sequence. A bit unusual though. 

 

My general concern is that FPGA PLL clocks have relative high jitter, not well suited as ADC clock if you have performance requirements for the ADC output.
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