Hi,I have to generate several clocks on Arria 10 SoC board. The clocks and their applications are as follows:
Hey Arvind,You could use a fPLL to generate the 3GHz clock and 1.5GHz clocks. Then cascade another PLL with this one and generate the 150MHz clock. You could use them in the source-synchronous mode or the Zero-delay mode and have their reset's tied together. Yes, the PLLs in this case may have different locking periods but that can't be avoided. Using one PLL for generating higher frequencies and another for the lower frequencies would be a good option.
Hi,Thank you for replying. The 1.5GHz and 3GHz outputs from fPLL and zero-delay mode 150MHz output from a cascaded PLL would work for me. However, I think it's not possible to generate a 150MHz clock output using a PLL from 1.5GHz clock. I also checked it: the transceiver PLL's don't supports outputs below 800MHz, while the IOPLL cannot take reference clock frequency more than 700MHz. Another option is to first generate a clock at 150MHz using IOPLL in zero-delay mode, and then use it as a reference clock to generate 1.5GHz and 3GHz clocks using an fPLL. However, the fPLL does not show the option to source-synchronize the outputs. Please let me know if you have any suggestions. Thanks.
No, there is no external clock here. I want to generate three synchronized clocks at frequencies 150MHz, 1.5GHz, and 3GHz; the first two would be used at the Arria 10 Transceiver PHY to send data at 3Gbps (1.5GHz), while the last one (3GHz) would be used to sample the received analog signal at external high-speed ADC. My question here is that how can I generate these three clocks such that they are synchronized. The synchronization is important to get the time of flight of the transmitted signal, which is essential for the application.Please let me know if you have any suggestions on how can I generate these clocks. I have tried several options (I have described them above) using the PLLs available for Arria 10 SoC, but they did not work for me.
--- Quote Start --- while the last one (3GHz) would be used to sample the received analog signal at external high-speed ADC --- Quote End --- Yes, that's my point. Where do you connect the ADC clock input?
I see. I was thinking of taking the output clock through the transceiver pins of the FMC connector. I think I'll have to use the clock on the ADC board for sampling then.However, the problem of synchronizing the 150MHz and 1.5GHz still remains.
Generating a clock signal on transceiver pins might be possible under circumstances by sending a constant 01010101 sequence. A bit unusual though.My general concern is that FPGA PLL clocks have relative high jitter, not well suited as ADC clock if you have performance requirements for the ADC output.