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What is the maximum clock speed, the maximum PLL speed, the maximum logic block input frequency and the minimum propagation delay through gates on the Cyclone 10 LP and GX FPGAs?

DMerc4
Beginner
‎11-22-2018 02:31 PM
1,143 Views

The more answers to the above questions I can get the better. Many thanks.

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Rahul_S_Intel1
Employee
‎11-23-2018 05:56 AM
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Hi,

The information you are seeking is available in the data sheet of Cyclone 10 Lp and cylone 10 gx

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10lp-51002.pdf

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10gx-51002.pdf

 

Regards,

RS

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