- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I'm developing for an Agilex 7 board which is equipped with about 36 Mbit of eSRAM and 146 Mbit of M20K. Since the M20K memory is both larger and has lower access latency than the eSRAM, what is the point of using the latter? Also, is it possible to get Quartus to infer eSRAM when using Intel OpenCL or DPC++?
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Björne,
For eSRAM IP you can refer to this document:
https://www.intel.com/content/www/us/en/docs/programmable/683241/23-2/embedded-memory-features.html
For memory size query, I think can refer to this link:
Thanks.
Regards,
Aik Eu
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Björne,
I will close the thread and transition it to community support if not further question?
Thanks.
Regards,
Aik Eu
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Björne,
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Thanks.
Regards,
Aik Eu
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page