What is the relationship between sop, pvalid, hvalid and dvalid signal in RTile IP?

[myrfy001]

Regarding the specific behavior of the sop, eop, hvalid, and dvalid signals in the RTile, the design differs from the previous PTile interface. The single valid signal in the PTile interface has been split into hvalid and dvalid in the RTile. According to Section 4.3.1.1 in the "ug20316 R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide" (referred to as the manual):

This is defined to enable pipelined Header/Prefix and Data transfers to meet the bandwidth target. For example, while transferring the Data for one TLP, the Header and Prefix for the next TLP can also be transferred.

 The exact meaning of the sop signal is not explicitly explained in the manual, and there are even contradictory statements. Thus, there are two hypotheses:

A. sop marks the start of a new TLP, meaning sop and hvalid always occur simultaneously.

B. sop marks the start of the data portion within a TLP, meaning sop and the first dvalid signal of a TLP always occur together.

Conflicting Points:

• In Table 56 of the manual, sop is described in relation to pX_rx_stN_eop_o and rx_stN_valid_o, but it's unclear whether rx_stN_valid_o refers to hvalid or dvalid. However, the example given ("For example, when asserted, rx_st2_sop_o signals the start of a TLP on rx_st2_data_o[255:0]") implies that sop is associated with dvalid, supporting Hypothesis B. This also suggests that if a TLP doesn't contain a payload, there would be no sop signal but an eop signal.
• In Table 58, sop is said to be asserted for one clock cycle per TLP and qualifies the corresponding tx_stN_hdr_i and tx_stN_tlp_prfx_i signals. This description indicates that sop should be high simultaneously with hvalid to ensure correct transmission of the TLP header, supporting Hypothesis A.
• If both Hypotheses A and B are true, the only scenario is that if sop, hvalid, and dvalid signals appear for a TLP, they must do so synchronously. This contradicts the description in Section 4.3.1.1, which allows the header to be transferred ahead of the data.

In summary, the manual's descriptions create ambiguity regarding the sop signal's behavior. Clarification from the manual's context or additional information is needed.

[ventt]

Hi myrfy001,

Thanks for reaching out.

Allow me some time to investigate your issue. I shall come back to you with the findings.

Thanks.

Best Regards,

Ven

[ventt]

Hi myrfy001,

I believe your question has been addressed through IPS.

Kindly refer to the IPS for the details.

In the R-Tile AVST interface, the Header and Data are separated. Therefore, for TLP that contains data, when the SOP signal is asserted, both the header valid and data valid signals are asserted simultaneously. For TLP that does not contain data, the SOP signal indicates that header valid.

Thanks.

Best Regards,

Ven

[myrfy001]

Thanks for your reply.

Infact, I did't pay for any IPS service so I only get the reply from your reply.

From your reply, it said that 

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for TLP that contains data, when the SOP signal is asserted, both the header valid and data valid signals are asserted simultaneously.

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It seems that this behaviour is conflict with the  section 4.3.1.1 in the "ug20316 R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide", which said :

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This is defined to enable pipelined Header/Prefix and Data transfers to meet the bandwidth target. For example, while transferring the Data for one TLP, the Header and Prefix for the next TLP can also be transferred.

To my understanding,  the text above addressed that the (header+payload) can be transmitted before the payload. For example, in the first beat, the header is transfered, and in the second beat, the payload is transfered. 

And we can also think it in another way, if both the header valid and data valid signals are asserted simultaneously, why split it into two different signals? why don't keep it the same as the PTile which only have one valid signal for both header and payload?

Thanks.

[ventt]

Hi myrfy001,

As there are no further inquiries, I will transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you.

After 15 days, this thread will be transitioned to community support.

The community users will be able to help you with your follow-up questions.

Thanks.

Best Regards,

Ven