I'm trying to do some side by side testing of an algorithm using a Cyclone III (EP3C16F256) and the Nios, Coldfire, and ARM Cortex-M1 processors. I hope to publish my findings for a class project.
This fpga board that I'm planning on has 15,408 gates, so putting a standard Nios (1300 LE), Arm (2600) and a coldfire (? LE -
www.ip-extreme.com/IP/coldfire_altera_v1.html ), shouldn't be a problem.. in theory.. however I haven't been able to find anyone doing something like this, so I'm not sure.
In the past, I've used a cyclone II (18,752 LE), with a single Nios ( and what I thought was very little logic) and quickly ran into issues where the design wouldn't fit!
I know using Logic elements, like Xilinx slices, can be a bit vague to predict actual usage, but anyone know the maximum number of processors that can reasonable be expected to route given a certain size fpga & processor(s)?
