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Hi,all
I have develop a system with two FPGA. the one is EP3C10 and the other is EP3C25. I config them by Multi device AS mode. the connect scheme is followed Figure9-4 of handbook of page175 Two different sof file must be loaded to them separately.the sof corresponding to the master device is come out by AS compiling. the sof corresponding to the slave device is come out by PS compiling. Now I convert two sof file into a pof file and then loaded into EPCS16 but neither of them work. After configuration, the message window of QuartusII will not show any error or warning. the nCEO of master device will not assert to low. then I configurate the master device only by separate the board trace of shared config_done and configuration is successful. What's wrong in my design? hope your good solution!Link Copied
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Is the nCEO pin defined as a regular I/O after configuration, or programming pin? It should be the latter.
In the assignments menu, go to device, click on the "Device and pin options" button, and go to the "dual purpose pins" section to check it out.- Mark as New
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--- Quote Start --- Is the nCEO pin defined as a regular I/O after configuration, or programming pin? It should be the latter. In the assignments menu, go to device, click on the "Device and pin options" button, and go to the "dual purpose pins" section to check it out. --- Quote End --- Thank Daixiwen at first. I check the nCEO pin followed your guidance and find that it is defined as programming pin in my preceding project compiling but it also lead to failure configuration. Is the project operate in master device must be compiled by AS mode and the project used in slave device be compiled by PS mode? or two of them are compiled by AS mode? The other need your check is how do i arrange the .sof file in the process of convert programming file. I open the convert programming file window and add sof data. so there page0 and page1 in the list. then I add file to them respectively. My question is whether i have to locate the sof come from master device to page0 and that of slave device located in page1 or not? Thanks and hope your reply!
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--- Quote Start --- the sof corresponding to the master device is come out by AS compiling. the sof corresponding to the slave device is come out by PS compiling --- Quote End --- I think the generation of sof does not require the setting of AS or PS during compilation. Only when you need pof, you need set either AS or PS in Configuration scheme under Device-> Device and Pin Options -> Configuration tab. (But make sure on hardware, the MSEL pins of master and slave devices are set to AS and PS respectively.) So in your case, compile your designs of master device and slave device and generate their sof files separately. When combining them with Convert Programming Files, add two sof files below Page_0 with master device sof on the top. Do not use Page_1. (First click Page_0 to highlight it, then click Add File.. button to add sof files, do not click Add Sof Data) And generate the pof file. This is how I do with my project, which is the same case as yours.
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--- Quote Start --- I think the generation of sof does not require the setting of AS or PS during compilation. Only when you need pof, you need set either AS or PS in Configuration scheme under Device-> Device and Pin Options -> Configuration tab. (But make sure on hardware, the MSEL pins of master and slave devices are set to AS and PS respectively.) So in your case, compile your designs of master device and slave device and generate their sof files separately. When combining them with Convert Programming Files, add two sof files below Page_0 with master device sof on the top. Do not use Page_1. (First click Page_0 to highlight it, then click Add File.. button to add sof files, do not click Add Sof Data) And generate the pof file. This is how I do with my project, which is the same case as yours. --- Quote End --- Thank wdshen a lot! your guidance makes the problem solved. Thanks again!

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