When using an external PLL, my Stratix V native PHY runs at double the intended rate

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

When using an external PLL, my Stratix V native PHY runs at double the intended rate

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Hello,

In my design I instantiate a Native PHY on a Stratix V, configured with direct PMA access (10 bit serialization factor) using an external PLL. The design works, though an odd thing occurs, in that the reference clock appears to be 'doubled' by the time it reaches the serialiser in the PMA. That is, if my external PLL runs at 100MHz, the high speed serial clock runs at 2GHz.

If I set the transmit PMA clock divider to 2, the design operates correctly, but I am curious why.

Is the PMA input double data rate for example? Where is the clock being doubled?

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