- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
I managed to take advantage of the ATLPLL in EP4CE15F256. I think I should assign the clock output pin to a dedicated single-ended pin named "PLL1_CLKOUTp", for outputting a reference clock from the PLL1 in my Cyclone IV FPGA. Trying to find such related information in cyclone iv handbook, however, I failed to find a clear pin Map which could tell me where THE PIN locates on my EP4CE15F256. Could you help me and told me where the PLL1_CLKOUTp pin is? Which document should I refer, in order to find such information? I am sincerely looking forward to your reply. Naroah Mar/03/2014Link Copied
4 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
I could find diff1_outclkp in my pin planner? Is that what I needed? https://www.alteraforum.com/forum/attachment.php?attachmentid=8534 Naroah Mar/03/2014- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
You have marked DIFFCLK_1p (M2), but you are searching for PLL1_CLKOUTp(R4).
Besides in Pin Planner, you'll find the information in device pinout files.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi FvM,
Oh, I've got it! It is the label "L" that indicates "PLL#_CLKOUTp/n"! Sorry for my ignorance, but where the "Device Pinout Files" is? I cannot find it in my Quartus II menu. Could you tell me? Naroah Mar/04/2014- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content

Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page