Why Clk Oscillator waveform is not square in the oscilloscope?

[Altera_Forum]

If some body knows please help me regarding these two below questions. 

1- Why board's Clock waveform is not square in the oscilloscope? As I am new I use this simple code:  architecture behavior of clk is begin  process (clk) begin  clk_out<= clk ; end process; end behavior;   2- I want to create a delay in my output signals, input is clk signal and outputs are signal "a" and signal "b"? I wrote such a below code. But in the oscilloscope I don't see any delay between signal a and b? How can I create delay in Clk signal and observe in the oscilloscope? I use 50 Mhz clock frequency and therefore every signal period is 20 ns and I have to see the delay easily but there is nothing in Oscilloscope?   library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity clk_delay is port ( clk_in : in std_logic;  clk_out_a : buffer std_logic;  clk_out_b : buffer std_logic  ); end clk_delay; architecture behav of clk_delay is  begin  p1: process (clk_in)  begin  clk_out_a <= clk_in after 5 ns;  clk_out_b <= clk_in after 15 ns;  end process;  end behav;   Regards

[Altera_Forum]

Hi there,  

regarding the waveform - I assume we are talking about the clk-Signal generated by the external 50MHz clock? That raises the question what kind of scope and probe you are using as these high frequencies cannot be shown on low-end scopes (according to Nyquist, you need at least two points per period for frequency information and 10 points for some estimation of signal's waveform. Thus 50MHz clock would require 500MHz scope (and matching probes / interconnection). Regarding the delay: The term "after x ns" cannnot be systhesized into the Hardware - it's a construct to be used for testbenches and/or simulation but not for real hardware. To implement delay you normally use a counter driven by "clk" with the delay being a multiple of "clk" periods. Using your's 50MHz, the smallest delay would be 1 clockcycle, i.e. 20ns... (Quartus should have raised a warning on the "after..."...  Regards

[Altera_Forum]

Thank you for information. My FPGA board is Cyclone II and it has three clock 50 Mhz, 27 Mhz and 24 Mhz. I am using the 50 Mhz clock now and I want to see the clock signal (normally it should be as a square waveform) but it is not square. Also as you said I am going to check the scope and probes. 

According to the delay could you please be more specific and if there is any examples guide me. Please introduce me links, references or extra information.  Thank you so much.

[Altera_Forum]

Regarding the delay I would suggest something like: 

 P1: PROCESS (clk_in) BEGIN if (delay_cnt_A < xyz)  then  clk_out_a <= '0';  delay_cnt_A <= delay_cnt_A+1;  else  clk_out_a <= clk_in; end if; ... END PROCESS; END behav  Thus the clk_out_a is constant until the delay_cnt_A has reached the configured "xzy" threshold, i.e. the configured number of clk_in cycles are elapsed... (Just as a rough idea of implementation...)