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Why PCIe R-tile report fitter error in Quartus 21.3?

Jiayi_H_Intel
Employee
71 Views

Hi expert,

Rtile design successfully passed the compilation in Quartus 21.2 and it can also linked up with host in board test.

But when I upgraded it to Quartus 21.3 and do a compilation, the fitter stage report errors:

 

 

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic pin in region (1, 173) to (1, 174), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): refclk_pcie_14c_ch0_p
Error (16234): No legal location could be found out of 2 considered location(s). Reasons why each location could not be used are summarized below:
Error (179009): Could not find enough available I/O pin locations that supports the Current Mode Logic (CML) standard (2 locations affected)
Info (175029): DR68
Info (175029): pin containing PIN_DR68
Info (175015): The I/O pad refclk_pcie_14c_ch0_p is constrained to the location PIN_DR68 due to: User Location Constraints (PIN_DR68) File: /nvme_disk/iocdev/avf2virtio/github/pcie_ed_golden/pcie_ed/pcie_ep.v Line: 29
Info (14709): The constrained I/O pad is contained within this pin
Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.

 

 

 

I used these pin assignment for ref clock in both 21.2 and 21.3:

set_location_assignment PIN_DM70 -to refclk_pcie_14c_ch0_n
set_location_assignment PIN_DR68 -to refclk_pcie_14c_ch0_p
set_location_assignment PIN_CR70 -to refclk_pcie_14c_ch1_n
set_location_assignment PIN_CU68 -to refclk_pcie_14c_ch1_p

 

Do you know why it cannot work on 21.3? If the pin assignment is wrong, what should it be like?

Thanks very much for your help!

 

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Jiayi_H_Intel
Employee
60 Views

Find the root cause:

ref clock type is assigned as: CURRENT MODE LOGIC (CML).

This assignment passed in Quartus 21.2, but got error in Quartus 21.3.

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