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Valued Contributor III
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Why change phase of PLL doesn't improve clock skew?

Dear all,  

 

I have an dedicated clock input to feed an main PLL and has too clock output with the same frequency, one clock output from the main PLL is to launch the finished data, the other clock is to feed the logic unit (which has its own PLL) to process data. There is -4.6 ns clock skew between the derived clock inside the logic unit and the first clock output from main PLL. I changed the phase of the first clock output which is responsible to launch finished data, want to improve clock skew. However, the clock skew doesn't seem to change.  

 

Anyone can help me? Thank you very much!
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