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Altera_Forum
Honored Contributor I
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Why happens the message "component" is outside the master's address range in QSYS?

In my course I'm designing a flash controller in FPGA and integrating everything with QSYS to load in the board and debug. I connected the controller I made with the clock through an avalon MM breach as it can be seen in the picture 

 

https://alteraforum.com/forum/attachment.php?attachmentid=14671&stc=1  

, I was getting the error message: 

 

"component" is outside the master's address range 

The data width of my flash is 24 bits. 

My teacher has fixed this by editing the breach and inputting a larger data width of 32 bits. And just told me, it has to be larger than the flash, but he did not clarify why and left. 

 

I wish to know the reason for this. thanks in advance.
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Altera_Forum
Honored Contributor I
267 Views

Hi, 

 

Can you re-attache image with the error,Not able to view the image attached. 

I have tried to generate error but not succeed,Can you provide me information like which all IP you used and screen short of address map tab. 

 

Check the link which may help, 

Answered by Daixiwen. 

https://www.alteraforum.com/forum/showthread.php?t=33226 

https://alteraforum.com/forum/archive/index.php/t-55243.html 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
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