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Altera_Forum
Honored Contributor I
1,837 Views

Width of Slave id(4) must be min 5. Increase slave ID width or reduce connected maste

Hello, 

I have used the Arria 10 Soc design from rocketboard to which I am making few modifications. I am getting the following error in qsys when I exceed a particular number of connections.(to HPS) 

The error is as follows: 

error: arria10_hps_f2sdram0_data: width of slave id signals (4) must be atleast 5. increase slave id width or reduce widths for any connected axi master 

I would like to increase the slave ID width to solve this error. Now where and which parameter I have to change so that I am able to solve this error? 

 

Thank you
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6 Replies
Altera_Forum
Honored Contributor I
240 Views

The error is with the hard memory controller interface. Did you add the Arria 10 External Memory Interface for HPS component to the system and connect it to the HPS after enabling the conduit required for its connection in the parameter settings?

Altera_Forum
Honored Contributor I
240 Views

Thank you sstrell for the reply.I have already done that. 

 

I am using the F2SDRAM bridge in my design.The F2SDRAM bridge doesn't work if the conduit for emif is not enabled in HPS. 

Any other idea? 

 

As i go on increasing the number of slaves connected to HPS, the error is being modified to the below: 

Error: arria10_hps_f2sdram0_data: Width of Slave ID signals (4) must be atleast 7. Increase slave ID width or reduce widths for any connected AXI master
Altera_Forum
Honored Contributor I
240 Views

Check the setup of whatever FPGA masters are connected to the bridge. Something is not matching up.

Altera_Forum
Honored Contributor I
240 Views

The ID widths of the masters connected to the F2SDRAM bridge exceeds the ID width (4) of the F2SDRAM bridge slave port. If you can, reduce the size of the masters connected to the F2SDRAM port. If you cannot do this, then place an AXI Bridge in front of the F2SDRAM bridge. You can set the ID width of the master interface (connects to the F2SDRAM bridge) to 4 and set the ID width of the slave interface (connects to your other masters) to a higher value.

Altera_Forum
Honored Contributor I
240 Views

Thank you sstrell and sslock for the information.The AXI bridge idea worked. I was able to take it through synthesis flow also without any error. 

 

Am I right in assuming only few slaves can connect to F2SDRAM at a time and hence the width of it is limited to 4?
Altera_Forum
Honored Contributor I
240 Views

 

--- Quote Start ---  

Am I right in assuming only few slaves can connect to F2SDRAM at a time and hence the width of it is limited to 4? 

--- Quote End ---  

 

 

To clarify, you are asking about the number of masters (not slaves) that will connect to the F2SDRAM port. The number of supported masters depends on their AXI ID width. 

 

If the masters have a width of 4, then only one can be connected. 

If the masters have a width of 3, then 2 of them can be connected (the "extra" ID bit is used to distinguish between the two masters). 

If the masters have a width of 2, then 4 of them can be connected (the extra 2 ID bits are used to distinguish between the 4 masters). 

If the masters have a width of 1, then 8 of them can be connected (the extra 3 bits are used to distinguish between the 8 masters).
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