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Altera_Forum
Honored Contributor I
767 Views

With Transceivers, High-Speed Source-Synchronous Differential I/O Interfaces - LVDS

is there any limitation in the cyclone 1o gx transceiver to create lvds signal defined as vocm 1.25 v , 0.3v to 0.4v differential swing with 2.5 gbps (1.25 ghz clock) by using the external shared clock with minimum 5 transceivers for source synchronous implementation ( 1 clock 4 data late at 2.5 gbps data rate with 1.25 ghz )?

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Altera_Forum
Honored Contributor I
40 Views

I believe that your question about LVDS standard in transceivers has already been answered in one previous threads of your Cyclone 10 GX series. 

 

Instead of repeating questions, you may want to study the document details in the meantime, e.g. about the difference between AC and DC coupled links.
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