Working on a PCB with a Cyclone IV E, some questions

[Altera_Forum]

Hello, 

 Past weeks I have been working on a PCB with a Cyclone IV E on it. I will be using either the EP4CE6 or the EP4CE10, they are interchangeable as far as I know. I am almost finished with my design, but I still have some questions:   

1. I have some unconnected pins, what should I do with these, leave unconnected? Some of these are clk pins. I read in an app note that the unused clk pins should be connected to ground. Should I connect them directly or via a resistor?  
2. I also have some pins going to an expansion header, so I can connect some external signals/inputs. I also have some clk pins going to this expansion header. This means that if I do not use the header (which is very likely) these clk pins will be left unconnected anyways. Therefore, what is the harm of leaving clk pins unconnected?  
3. I do not have an oscillator on my board. I am planning to tap a clk signal from another PCB (which I have successfully done with a development board, I have a working prototype). This means that if I do not connect my FPGA to the other PCB I will not have a clk input. Is a clk input necessary on one of the clk pins, to program the FPGA via JTAG for instance? I suppose not, because JTAG also holds a clock signal. My question is more or less, will the FPGA do its normal functions without a clock signal on one of the clk inputs (loading a design via JTAG, or via EPCS4 flash, obviously only combinational designs would work without a clock input)?  
4. My design is using a single data rate SDRAM. In some designs I have seen, they use pull-up resistors on some of the pins (CKE, CS_n, WE_n, CAS_n, RAS_n). Some designs did not have these. Are these pull-up resistors necessary? What is the point of them? My design currently does not have them and I have limited space, so it would be nice if I could do without.  

  That is all I can come up with for now. I think I will post some pictures of the design later, so perhaps people can see if my routing principles are correct. Thanks in advance!

[Altera_Forum]

Hi, 

well here are some answers to your questions...  ad 1) the recommendation in the handbook is to connect all unused Pins to ground in Hardware and turn the same Option on in the Quartus Software. This "simulates" the device would have more ground Pins resulting in better current Distribution (more Pins). I always left These Pins open in HW and turned the "tri-state with weak pull up" Option in Quartus. If you connect unused Pins to gorund in Hardware be sure to match HW with the programming file to prevent any Pin driving a Signal in your Programm code while being connected to HW...   ad 2) any clock line like any Signal line as well is an antenna and may - if left "open" - cause voltage overshoot or undershoot due to Reflexion. If you manage to match clock line impedance (length and Routing of trace on pcb) and clk frequency this may result in voltage Level exceeding the specification reducing the life time of your FPGA. To prevent this you should either provide a footprint for a pull or series resistor (or take care of the Routing / measure the Signal in real HW to check if there are any exceeding over-/undershoots)  ad 3) Neither JTAG nor EPCS4 configuration require an on board oscillator. JTAG uses the JTAG "TCK" clock Signal while the DCLK Signal for the EPCS4 configuration Interface is generated by the FPGA itself. Any design w/o dedicated clock can only be combinatorical logic, but the FPGA can be programmed and operated w/o external oscillator  ad 4) I would argue using pull resistors is mainly to provide a stable Signal on the line during the configuration cycle (FPGA Pins tristate) and provide a known load to stabilize signals (over- undershoot issue like for 2) question).  Hope that helps a Little :-) Carlhermann

[Altera_Forum]

--- Quote Start ---  Hi, well here are some answers to your questions...  ad 1) the recommendation in the handbook is to connect all unused Pins to ground in Hardware and turn the same Option on in the Quartus Software. This "simulates" the device would have more ground Pins resulting in better current Distribution (more Pins). I always left These Pins open in HW and turned the "tri-state with weak pull up" Option in Quartus. If you connect unused Pins to gorund in Hardware be sure to match HW with the programming file to prevent any Pin driving a Signal in your Programm code while being connected to HW...   ad 2) any clock line like any Signal line as well is an antenna and may - if left "open" - cause voltage overshoot or undershoot due to Reflexion. If you manage to match clock line impedance (length and Routing of trace on pcb) and clk frequency this may result in voltage Level exceeding the specification reducing the life time of your FPGA. To prevent this you should either provide a footprint for a pull or series resistor (or take care of the Routing / measure the Signal in real HW to check if there are any exceeding over-/undershoots)   --- Quote End ---   I synthesized the design with the pin placement just now. I have taken a look at the generated .PIN file. For all the normal unused I/O it says it will use "reserved input with weak pull up". In one of the app notes I read that if DEV_CLRn and DEV_OEn are unconnected they should be tied to ground. In the .PIN file they are however of the type reserved input with weak pull up. Isn't there going to be running a small current now?  For my unused CLK inputs it says they are of the type "GND+". These include the unused CLK inputs on the expansion header, because currently I am not using these. The .PIN file describes the type "GND+" should be connected to GND. But it can also be connected to a valid signal on the board. I guess this means the CLK inputs should not be left floating. I suppose I can connect the CLK pins that are not used for my expansion header directly to ground (so not with a resistor in series)?   I suppose that if the CLK inputs are unused on the I/O header I should provide a PULL DOWN resistor to ground on those lines? I guess I can use one resistor to provide the PULL DOWN for both the CLK inputs on my expansion header?    --- Quote Start ---   ad 3) Neither JTAG nor EPCS4 configuration require an on board oscillator. JTAG uses the JTAG "TCK" clock Signal while the DCLK Signal for the EPCS4 configuration Interface is generated by the FPGA itself. Any design w/o dedicated clock can only be combinatorical logic, but the FPGA can be programmed and operated w/o external oscillator   --- Quote End ---   Allright, just as I thought. This is completely clear now to me.    --- Quote Start ---   ad 4) I would argue using pull resistors is mainly to provide a stable Signal on the line during the configuration cycle (FPGA Pins tristate) and provide a known load to stabilize signals (over- undershoot issue like for 2) question).  Hope that helps a Little :-) Carlhermann  --- Quote End ---   I will leave these away for the time being. I can always hand solder some pull ups and correct the design afterwards.

[Altera_Forum]

Hi, 

if you use the General control signals DEVn and OEn, tying them to GND would enable the Output and clear the I/O, thus any pin would be at least in a defined Level. If you do not use These Pins, I think at least OEn should be tied to GND, but that maybe my personal habbit. The small current - tying the signals to GND with the weak pull - will be very small compared by the normal Operation current the design will consume.   The CLK Signals however feed a dedicated clock routing network, thus these are internal routes running across the complete chip and would spread any noise picked up also across the complete chip. thus it is a good idea to take care of the unused clock network lines to be connected to GND. If you do not intend to use the not connected clock lines, you may connect both together with a pull-down to GND.   Kind regards :-)