Writing via an Avalon MM Master to an On-Chip M4K

[Altera_Forum]

Hello, 

 I have the following Nios II architecture. A custom component (ADC controller) implements an Avalon MM master that is connected to the Avalon MM slave of an On-Chip RAM. I have the following questions:  1. Should it be possible to store a word at each clock cycle? 2. Does the master have to use a burst signal? Currently it doesn't and the first few words are misaligned - I just assert the "write" signal and then at each clock cycle change the "writedata" and "address" signals.  Thanks,  -- Alex

[Altera_Forum]

1. not each clock. 

it is depending on the clock. you can not write all data in each clock. even you use burst-transfer. but if you use different clock. i.e) ADC controller is 10MHz and AvalonMM clock is 50MHz. you may be able to send 20 MB/sec data without loosing data.  2. burst transfer if you need fast transfer(always depends on how much) you may need burst transfer.