XAUI IP Core compilation problem

[Altera_Forum]

Hi, 

I am designing a state machine to send a UDP packet through XAUI. The packet will be divided into 72 bits and reach a XAUI PHY IP Core produced by Megafunction. So basically it is not so complicated. In overall, all I need is a state machine that divides data into 72 bits and a XAUI PHY IP Core that receives data from the state machine.  The problem that I now faced is, when I try to compile, it shows this error message  Warning: RST port on the PLL is not properly connected on instance pll_156_25:my_pll_156_25|pll_156_25_0002: pll_156_25_inst|altera_pll:altera_pll_i|general[0].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock.  Info: Must be connected Error: HSSI PMA RX Buffer node 'xaui_ip_core:my_xaui_ip_core|altera_xcvr_xaui:xaui_ip_core_inst|cv_xcvr_xaui:alt_xaui_phy|av_xcvr_low_latency_phy_nr:alt_pma_0|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[3].rx_pma.rx_pma_buf' is not properly connected on the 'DATAIN' port. It must be connected to one of the valid ports listed below.  Info: Can be connected to O port of arriav_io_ibuf WYSIWYG  Info: Can be disconnected Warning: RST port on the PLL is not properly connected on instance pll_156_25:my_pll_156_25|pll_156_25_0002: pll_156_25_inst|altera_pll:altera_pll_i|general[1].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock.  Info: Must be connected Error: HSSI PMA TX Buffer node 'xaui_ip_core:my_xaui_ip_core|altera_xcvr_xaui:xaui_ip_core_inst|cv_xcvr_xaui:alt_xaui_phy|av_xcvr_low_latency_phy_nr:alt_pma_0|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[2].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_buf.tx_pma_buf' is not properly connected on the 'DATAOUT' port. It must be connected to one of the valid ports listed below.  Info: Can be connected to I port of arriav_io_obuf WYSIWYG    Since I am just using the IP Core made by Megafunction without any modification, I have no Idea where I should fix. I tried to go deep inside into the code of the IP Core, but the entire codes were way too much complicated.  Is there anyone who knows something about this problem? Any help would be appreciated, please.

[Altera_Forum]

The errors are not pointing at anything 'deep inside into the code of the IP core'. On the face of it they're pointing at the way in which you have (or haven't) connected up 3 ports. 

 Take the first - the PLL reset port. It looks like that is referring to a PLL you have created and not one contained in the XAUI core. It doesn't like the way in which you are driving the 'RST' port on it. Are you driving the reset port?  The same can be said for the 'DATAIN' port on the XAUI interface. This port name refers a name buried in the IP core but ultimately emerges at the top level. Again, what have you connected this to? Have a look at the the 'DATAOUT' port error in the same way

[Altera_Forum]

Thank you very much ! 

As you said, the problem was the incorrect port connection at the top level. So Analysis and synthesis was successful. However, I faced another error that is,  Error (177035): The input pin hsma_rx_n[0] assigned to HSSI Pin_U1 has no fanout. Error (177035): The input pin hsma_rx_n[1] assigned to HSSI Pin_R1 has no fanout. Error (177035): The input pin hsma_rx_n[2] assigned to HSSI Pin_N1 has no fanout. Error (177035): The input pin hsma_rx_n[3] assigned to HSSI Pin_L1 has no fanout.  I have connected the positive pins directly to the DATAIN port of the IP Core. But I don't really know where I should connect the negative ones to. Probably a voltage value of (negative - positive) should be the correct one to go into the DATAIN port instead of only the positive one itself. However I couldn't figure out how to subtract a voltage signal from another. Your helpful advise would be greatly appreciated again.

[Altera_Forum]

The negative pins should automatically be connected - providing you have constrained your design correctly. This includes specifying the relevant I/O standards for all the pins in the design. When you specify a differential I/O standard for a pin and assign a pin location (to the positive driver/receiver), Quartus will automatically assign the negative pin for you. 

 So, I suspect you've not specified a differential I/O standard for the pins you've listed.

[Altera_Forum]

Thank you very much for kind answer. 

However, I think I correctly specified the I/O standards by setting them to 1.5-V PCML. And they are all paired in p and n as shown in Pin Planner. I simply connected all hsma_rx_p pins to the DATAIN and hsma_tx_p to DATAOUT. According to the error messages, hsma_tx_p doesn't seem to have a problem, but only rx does.

[Altera_Forum]

Oh I just fixed the problem. It was the hsma_rx_n pins that I declared on the top, which I shouldn't have. 

But same as always, I faced another error again. I'd better organize it in a new post.  Thank you very much for help :)