Your question is ambiguous.
Many boards have more than one crystal on it. For example, my DE1 board has a 24 Mhz, 27 Mhz, and 50 Mhz crystal on it. They are easily found on the board's schematic.
A pll may be used to multiply or divide any of these clock signals that are fed into the dedicated clock inputs of the FPGA, or they may be used as is.
So the question is what clock are you interested in? The clock that goes to an audio chip, SDRAM, Video controller, NIOS 2's system clock, .....?
Assuming you want to know what the NIOS 2's system clock is, you need to find out what signal drives the signal named "clk" in the system instantiation in the top-level HDL file. If it is the output from a PLL, open up the megawizard and choose this existing PLL, and check the parameters there. You will then find the source clock's frequency and the output frequency.
If your top level module is a Quartus schematic file, the parameters used for the PLL are visible in a table somewhere on the schematic sheet.
