a question about rapidio 1x

[Altera_Forum]

Dear: 

Now I want to use rapidio 1x to communicate with TMS320C6455, The FPGA is stratix V.  I don't want to use Qsys, so i use Avalon-ST Pass-Through Interface to instead it. is it right?   From the RapidIO MegaCore Function, Table 5–23 show that gen_rx_data and gen_tx_data is 64bit or 32bit depend on the lane mode.In my design, i use 1x mode so the gen_rx_data and gen_tx_datashould be 32bit, but i can't find the definition of 32bit gen_rx_data and gen_tx_data, there is only definition of 64bit gen_rx_data and gen_tx_datafrom Table 4–18 and Table 4–19. Who can tell me the definition of 32bit gen_rx_data and gen_tx_data?   Sorry, my english is not good, Thank you! 

[Altera_Forum]

By default, Avalon-ST transfers the first symbol (byte) in the MSB of the data. Looking at the header for gen_tx_data from the table, with an 32-bit interface, "ackID" is going to be on bits [31:27] of the first word of the transfer, while "sourceID" is going to be on bits [31:16] of the second word of the transfer. 

 In other words, the fields come in the same order (working from MSB->LSB ), you just need 2x as many cycles to transfer the data.

[Altera_Forum]

thanks, i will try!

[Altera_Forum]

--- Quote Start ---  By default, Avalon-ST transfers the first symbol (byte) in the MSB of the data. Looking at the header for gen_tx_data from the table, with an 32-bit interface, "ackID" is going to be on bits [31:27] of the first word of the transfer, while "sourceID" is going to be on bits [31:16] of the second word of the transfer.  In other words, the fields come in the same order (working from MSB->LSB ), you just need 2x as many cycles to transfer the data.  --- Quote End ---    The Figure 4–32 is a NREAD example. If i want to use SWRITE, what is the the format of gen_tx_data Bus. I know the Ftype and Ttype should be changed, but i can't find the Destination Address(not deviceID). In RapidIO II MegaCore Function, Table 4–25 give the formate of gen_tx_data very clear, but i can't find the formate of gen_tx_data in RapidIO MegaCore Function. Looking forward to your reply! Thank you!

[Altera_Forum]

http://www.alteraforum.com/forum/attachment.php?attachmentid=9560&stc=1  

This is a signaltap about TMS320C6455 send 256B data to FPGA by a SWRITE packet. sourceId : EE destinationId : F0 ftype : 6 address : 88888888 Now, if i want to send 256B data to TMS320C6455 by a SWRITE packet, what i should write the address in gen_tx_data

[Altera_Forum]

https://www.alteraforum.com/forum/attachment.php?attachmentid=9567  

This is a signaltap about TMS320C6455 send 256B data to FPGA by a SWRITE packet. sourceId : EE destinationId : F0 ftype : 6 address : 88888888 Now, if i want to send 256B data to TMS320C6455 by a SWRITE packet, what i should write the address in gen_tx_data

[Altera_Forum]

I believe the TI SRIO just connects to the SCR, so see the TMS320C6455 data sheet Table 2-2 Memory Map Summary. 

 The Altera AN513 app note targets E0000000 for the DDR2, so that is probably a good starting point.

[Altera_Forum]

I solved the problem, thank you!