about decimation

[Altera_Forum]

why do we need decimation in DDC,before the data go into the FIR digital filter,whose rate is fast.assume that the sample rate is 105MHZ,the single bandwidth is 40MHZ,if i need FIR to select 8MHZ's bandwidth from 40MHZ, is it ok,can the fir permit fast clock rate?how fast rate the fir can work.

[Altera_Forum]

--- Quote Start ---  why do we need decimation in DDC,before the data go into the FIR digital filter,whose rate is fast.assume that the sample rate is 105MHZ,the single bandwidth is 40MHZ,if i need FIR to select 8MHZ's bandwidth from 40MHZ, is it ok,can the fir permit fast clock rate?how fast rate the fir can work.  --- Quote End ---    Your questions are far from clear. In a DDC you normally receive signal at high sample rate e.g. 105Msps (if I understood you). Your target sampling rate is then decided by what signal you are working with. If your final signal bandwidth is 8MHz(complex) then a sampling rate of 8Msps may be what you aim at. This should cover +/- 4MHz provided your signal is around 0 frequency(baseband).

[Altera_Forum]

--- Quote Start ---  why do we need decimation in DDC,before the data go into the FIR digital filter,whose rate is fast.assume that the sample rate is 105MHZ,the single bandwidth is 40MHZ,if i need FIR to select 8MHZ's bandwidth from 40MHZ, is it ok,can the fir permit fast clock rate?how fast rate the fir can work.  --- Quote End ---    Decimation allows you to minimize the "work" required by your DSP logic.   The simplest way to process your data would be to multiply it with a complex-valued exponential (an NCO cos + sin outputs) with an NCO frequency centered on your band of interest, and then FIR filter that data. The resulting signal would still be sampled at 105MHz, but there would be no signal outside of your complex-valued baseband 8MHz bandwidth (-4MHz to +4MHz).  The problem with this simplistic approach is that you're clocking your DSP logic much faster than it needs to be, so you're burning power. If you only have 8MHz of "information", then you can reduce the sample rate to 8MHz. You can do this with your simple data set by throwing away samples, eg., 105MHz/8MHz = 13.125, so if you sample at 13x8MHz = 104MHz, you could throw away 12 of every 13 samples. That step is "decimation", or more generally "down-sampling".  The key to understanding decimation and multi-rate filters is realizing that "If you are throwing away samples, why bother doing the work associated with calculating those samples?"  The decimation operation can be moved through the DSP processing chain to the beginning, so that your FIR filter, and your NCO can operate at 8MHz.  If you wanted to extract all 5 x 8MHz channels from within your 40MHz band, then you could use a "polyphase filter", which is essentially a decimated FIR filter followed by an FFT.  When processing/decimating data, its often easier to deal in factors-of-2. There is a very efficient class of filters known as half-band filters. These filters allow you to change the data rate in factors-of-2 (other decimation factors can be implemented). In the case of your 8MHz signal bandwidth, the factors of two are; 16MHz, 32MHz, 64MHz, and 128MHz. If your 40MHz bandwidth is adequately sampled when operating the ADC at 64MHz, then you can use half-band filters to reduce the sample rate from 64MHz to 32MHz, 16MHz, and then 8MHz. A single NCO could be used at the first stage, or you can use a coarse resolution NCO to center the signal, and then use an NCO at the second-to-last state to center the band.  Read these notes for more details on DSP with FPGAs;  http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104paper_hawkins.pdf  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Decimation allows you to minimize the "work" required by your DSP logic.   The simplest way to process your data would be to multiply it with a complex-valued exponential (an NCO cos + sin outputs) with an NCO frequency centered on your band of interest, and then FIR filter that data. The resulting signal would still be sampled at 105MHz, but there would be no signal outside of your complex-valued baseband 8MHz bandwidth (-4MHz to +4MHz).  The problem with this simplistic approach is that you're clocking your DSP logic much faster than it needs to be, so you're burning power. If you only have 8MHz of "information", then you can reduce the sample rate to 8MHz. You can do this with your simple data set by throwing away samples, eg., 105MHz/8MHz = 13.125, so if you sample at 13x8MHz = 104MHz, you could throw away 12 of every 13 samples. That step is "decimation", or more generally "down-sampling".  The key to understanding decimation and multi-rate filters is realizing that "If you are throwing away samples, why bother doing the work associated with calculating those samples?"  The decimation operation can be moved through the DSP processing chain to the beginning, so that your FIR filter, and your NCO can operate at 8MHz.  If you wanted to extract all 5 x 8MHz channels from within your 40MHz band, then you could use a "polyphase filter", which is essentially a decimated FIR filter followed by an FFT.  When processing/decimating data, its often easier to deal in factors-of-2. There is a very efficient class of filters known as half-band filters. These filters allow you to change the data rate in factors-of-2 (other decimation factors can be implemented). In the case of your 8MHz signal bandwidth, the factors of two are; 16MHz, 32MHz, 64MHz, and 128MHz. If your 40MHz bandwidth is adequately sampled when operating the ADC at 64MHz, then you can use half-band filters to reduce the sample rate from 64MHz to 32MHz, 16MHz, and then 8MHz. A single NCO could be used at the first stage, or you can use a coarse resolution NCO to center the signal, and then use an NCO at the second-to-last state to center the band.  Read these notes for more details on DSP with FPGAs;  http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104paper_hawkins.pdf  Cheers, Dave  --- Quote End ---     thank for your answer,but i still have a question.provided that my AD'S sample rate is 105MSPS and signal bandwidth is 40MHZ,i want to use channel selective digital filter to select one of five channel(40/5=8),is it ok to accomplish the design in hardware(FPGA) with so high sample rate.if impossible,can you tell me other ways to achieve the idea.