about verify failed in sdram

[Altera_Forum]

hi,when i debug my program in niosII, i select the option Download program to Ram in Debugger page, but it always tips in the Console  

"Verifying 01000020 ( 0%) Verify failed between address 0x1000020 and 0x10081E3 Leaving target processor paused" (as my sdram is set at this address) i don't kown why. Is there any problem with my configure ? Normally how we optimize our configure settings.

[Altera_Forum]

It means your SDRAM interface isn't working for some reason (probably timing). I don't know what chip you are using but my approach is usually to create a piece of onchip memory in your SOPC system and run the NIOS out of the onchip memory. Then write a tiny piece of test code that exercises your SDRAM interface. You can also use the mem_test example application. 

 Jake

[Altera_Forum]

hi, now the verify is ok. but when i enter the debug page, it always shows"Thread [0](running)", so in this case i can't debug by step over/in. how i will do to solve this problem?

[Altera_Forum]

what's problem with your sdram? 

how you figure it out? i also have the same problem

[Altera_Forum]

I'd still try to run the memtest from on chip memory to fully test the SDRam. 

Having said that, I've already done all that and my program works fine from on chip ram, but I can't run from SDram. The program loads just fine, but I get the "Thread [0](running)" message as well, which basically means you've lost control of the processor.

[Altera_Forum]

I am getting the same problem: "Verify failed between address ..." when trying to use sdram. it works with on-chip ram, but i want to conserve my on-chip ram for other parts of my design.  

 did anyone find the solution?  thanks, -ben

[Altera_Forum]

... actually in a thread close by called "ddr2 sdram" user adream307 mention something that solved my problem: 

 "The clock for ddr2 sdram controller has 0 degree phase, but the clock for ddr2 sdram write has -90 degree".   I had changed the phases to match my original design.

[Altera_Forum]

Hello. 

I am using quartus 8.1 Device cyclone3 ep3c80f780-C7 and SDRAM mt48lc2M32B2. I am also geting the same problem of verify address failure. I don't know where to debug. I have seen it with some phase shifts but no success. Please guide me as i am stuck.   Thanks in advance. Regards.

[Altera_Forum]

Saranshmeh,  

 What does your design look like? Are you also trying to modify the standard design and get it to work? Does the standard factory NiosII design that came with the board work?   I started with the factory design, then slowly made changes to it to reflect my requirements for my design.   To fix the SDRAM timing, I just matched my settings exactly to the settings from the factory design in the SOPC Builder.   -Ben

[Altera_Forum]

Hi,  

May I know where to find the factory settings for the SDRAM timing? I facing same problem also where -3ns does not work. Thanks.

[Altera_Forum]

Hello, 

 I remember I had some similar problem, and it was because my computer had not enough memory, and I closed the other programs, messenger, internet explorer, etc. And it worked. Bye.

[Altera_Forum]

actually you can have a reference at demo projects from the "CD" in the development kits.

[Altera_Forum]

For the factory settings, I referenced the example designs that were put on my HDD when I installed Quartus II. For me, they are located at: C:\altera\90\nios2eds\examples and I referenced the designs in the vhdl directory of that folder. 

 Hope this helps!