accelerate cyclone V

Altera_Forum · ‎07-12-2016

Hi All,

I am using cyclone V SOC kit from Terasic.

Currentlly, I am using AXI bridge to communicate between FPGA and HPS; but I found this bridge seems to funcation with low latency. I made hps to fpga bridge connection for Light weight hps to FPGA communication.

Now I want to improve throughput and letency of communication between HPS and FPGA. any one can please suggest me to do so??

P.S : I go through exaple of Datamover; so I have another question that Is it necessary to use NIOSII Qsys componebt; if yes then could anyone explain How Nios II help to improve communication between h2f and f2h?

Thanks in advance.

Altera_Forum · ‎07-21-2016

The highest speed interface is FPGA-to-SDRAM because you get multiple ports and in the case of Cyclone V SoC you can gang them together to make a wider interface.

You might find this design to be useful if you don't have plans on having a Nios over on the FPGA side of the device, unfortunately it only targets Arria 10 SoC though: https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-example.html