adders and carry chains

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

adders and carry chains

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Hello.

According to Cyclone datasheet the logic elements can work in arithmetic mode so we can me make adders with very fast carry chains. I made 2 projects with Quartus II 10.1 Web Edition:

a - in the first I used Cyclone 1 EP1C3T100C8N. The technology map viewer ( post-fit ) showed the LE in arithmetic mode and the carry chains. That's Ok.

b - the second I used Cyclone 2 EP2C5T144C8N. I see the tech map viewer but it's not clear to me if the LEs are in arithmetic mode. But the Quartus didn't use the carry chain. It's like a ripple carry adder. Why?

The vhdl code are the same in both designs. It happens with other devices too.

I posted the code and the capture of the technology map schematics.

Thanks.

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