altclkctrl and state machine outputs

[Altera_Forum]

I am trying to drive the clkselect signal from the output of a statemachine  

called adc_clksel however the compiler thinks that adc_clksel is a constant signal and I'm not sure why ??? Heres the Error and I am able to control the clk select block driven by another signal. I am using QII v9.0 and my device is Cyclone III   Error: inclk[1] port of Clock Control Block "TDR_FSM:TDR_FSM_1|tv220_clk_mux:ADC_clk_sel_inst|tv220_clk_mux_altclkctrl_9nd:tv220_clk_mux_altclkctrl_9nd_component|clkctrl1" cannot be used when clkselect port is not used or is a constant   Heres an overview of what Im doing I have edited the statemachine for brevity    signal adc_clkselect, clksel : std_logic;     ADC_clk_sel_inst : tv220_clk_mux PORT MAP ( clkselect => adc_clksel, inclk0x => adc_clk(0), inclk1x => adc_clk(1), outclk => HS_ADC_clk );   process( CNTRL_STATE, AE_PhaseDone, trigger, ControlReg(14) )  begin case CNTRL_STATE IS   when IDLE =>  adc_clksel <= '0' ; if trigger = '0' then  NX_CNTRL_STATE <= IDLE ;  else NX_CNTRL_STATE <= ZERO_PHASE ; end if;   when ZERO_PHASE => -- Acquire data from A2D counter_select <= b"100" ; adc_clksel <= '0' ; AEng_start <= '0';   if AE_PhaseDone = '1' then -- DONE NX_CNTRL_STATE <= ONE_EIGHTY_PHASE ;  else NX_CNTRL_STATE <= ZERO_PHASE ; end if;   when ONE_EIGHTY_PHASE =>  counter_select <= b"101" ; adc_clksel <= '1' ; if AE_PhaseDone = '1' then  NX_CNTRL_STATE <= IDLE ;  else NX_CNTRL_STATE <= ONE_EIGHTY_PHASE; end if; when OTHERS =>  NX_CNTRL_STATE <= IDLE ; -- Full trace complete  end case;   end process;