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altddio_out in Cyclone III FPGA Development Kit

Altera_Forum
Honored Contributor II
‎09-15-2014 04:42 PM
1,088 Views

Hello!  

I encountered the following problem. When you try to transmit data over Ethernet in 1000, the output is constantly 0.  

 

 

I use to break altddio_out to break feed stream 8-bit words in the 4-bit. Connected as follows:  

 

 

altddio_out diff_out( 

.datain_h(MAC_out[7:4]), 

.datain_l(MAC_out[3:0]), 

.outclock(enet_gtx_clk), 

.dataout(ddr_out) 

); 

 

wire [3:0] ddr_out; 

 

 

top top ( 

.enet_tx_d(ddr_out), 

.enet_tx_dv(MAC_out_v_del), 

.enet_gtx(enet_gtx_clk), 

..... 

 

); 

 

 

enet_tx_d always = 0; 

 

How fix it?
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Altera_Forum
Honored Contributor II
‎09-16-2014 11:57 AM
432 Views

or must use only altera_tse megafunction?

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