altera pci host bridge sample

[Altera_Forum]

--update 20060327, I wrote a uClinux driver for the altera pci host bridge, check 

http://forum.niosforum.com/forum/index.php?showtopic=3174 (http://forum.niosforum.com/forum/index.php?showtopic=3174)  This is a sample design for NIOS2 with Altera PCI host bridge to connect external pci devices, such as WiFi, GigaLAN etc. It uses the sopcflow in the pci compiler. The sample design uses external PCI clock, and internal bus arbitor to support up to 2 external PCI masters. The sdram on avalon bus can be accessed by the external masters. A simple external interrupt wrapping module, "irqn", is used to connect interrupts from external devices to NIOS2.  Follow the user guide to add PCI timing constrain with the tcl file.  If you are new to PCI, read the book "PCI System Architecture" from MindShare.  The cpu access pci slave via PCI_Bus_Access base address, it was defined in the PCI toolbench page 4,Avalon configuration. They are divided into Configuration,IO,Memory space 1 and 2, each of 1Mbytes.  #define pcicfg_space (na_pci_compiler_0_PCI_Bus_Access)  // avalon space# define pciio  (pcicfg_space+0x100000)    // pci io device base in avalon space# define pcimm  (pcicfg_space+0x200000)    // pci mem device base in avalon space  // idsel of ad11=dev0,ad12=dev1  , using type 0 config request# define pcicfg(dev,fun,reg) (pcicfg_space | ((dev)<<11) | ((fun)<<8) | (reg))    // cfg space   You should configure and enable dev0,bar0 for external pci devices to access the sdram, eg base addr 0. You should configure external pci device's IO or MM bar within the windows which we setup in toolbench page 4. I had assigned both address space(to from pci) to be the same. Remeber to "uncache" the access.  Wire connection lists: (the suffix of pci pin name are omitted, the NIOS2 with pci core are called "cpu")  connect the idsel with resistve couple, cpu's dram will be device0 1. ad[11] -- 330R -- idsel of cpu (or it can be internal connected in the cpu) 2. ad[12] -- 330R -- idsel of pci device 1 3. ad[13] -- 330R -- idsel of pci device 2  connect the irqs line 1. the inta of cpu , no connect 2. each int of pci devices connect to a irqn input.  connect the req/gnt pairs from each pci devices to cpu pci clock should match length. other signals are bused. add pullup to all signals, except for ad . par needs pulllow.  Attached is the sample ptf and verilog design file for a cycloneii.  [attachment=53:attachment]