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altera_reset_synchronizer_int_chain_out

Altera_Forum
Honored Contributor II
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Hi all 

i builted a large design for Startix IV 530. 

i'm using up to 630 DSP blocks in my design. 

if let it run (compile) normaly, i get "altera_reset_synchronizer_int_chain_out" timming falling paths. 

if i add set_false_path command to my project SDC file, i get an error about the amount of DSP blocks 

"can not find legal placement for <x> dsp blocks". 

how can i solve this issue? 

 

inon_y
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Altera_Forum
Honored Contributor II
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Hi,  

how are you setting the false path?
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Hi,  

how are you setting the false path? 

--- Quote End ---  

 

 

set_false_path \-from {..|altera_reset_synchronizer_int_chain_out} \-to [all_registers]
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Altera_Forum
Honored Contributor II
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That's not good, your just sweeping issues under the "false path" rug. 

You should set a false path between the reset input signal and the synchronization registers _IF_ the reset signal is asynchronous in respect to the target clock. 

 

If you still get failing paths after that, then you have a problem that affects timing and you need to take care of it that way. 

Maybe the reset output needs to be driven to a global clock signal and Quartus is failing to do so automatically?
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