arria 10 lvds serdes

[LLCC]

hello,

I was originally using the quartus 17.1 Standard Edition to complete some designs that include LVDS SERDES IPs, and the projects were able to pass compilation successfully. However, when I migrated these projects to 22.1 Pro, compilation errors occurred, even though I am certain that the designs are identical to the original versions.

Here are one of the details of the error messages encountered：

Error(129015): Output port RXDATA on atom "data_rx_top_u0|one_rx_module_u3|lvds_rx_u0|chan17_u0|lvds_0|core|arch_inst|channels[9].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive, is not legally connected and/or configured
Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected
Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected
Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected
Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected
Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected
Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected
Info(11951): Module instance "data_rx_top_u0|one_rx_module_u3|lvds_rx_u0|chan17_u0|lvds_0|core|arch_inst|channels[9].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 6 connected to TXDATA port.

"I am very sure that the code is correct, and it compiled and passed simulation successfully in the 17.1 Standard Edition. Why am I encountering compilation errors in 22.1 Pro?"

[LLCC]

hello,How can I send my project to you privately? Please help me review it to see where the errors are. I really can't find the problem. Thank you.

[HortumNecmi]

Hello, I am having a similar problem, did you solve the problem? 

[AqidAyman_Intel]

We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum cases, along with others, did not get through as intended. As a result, we have a backlog of cases that we are currently working through one by one.

Please be assured that we are doing everything we can to resolve this issue as quickly as possible. However, this process will take some time, and we kindly ask for your patience and understanding during this period. The cases will be attended by AE shortly.

We appreciate your patience and understanding, and we are committed to providing you with the best support possible.

Thank you for your understanding.

[AqidAyman_Intel]

Hello,

Can you try to regenerate the Altera LVDS SERDES Receiver IP?

Or else, you can try to connect them up in your design.

[LLCC]

Thank you. I have already solved this problem. My feeling is that when the data output by this IP is being processed logically, it requires data from all channels to be used together. For example, if I only use the output data from a single channel to complete a certain logical process, while the output data from other channels is used for another logical process, it may trigger the aforementioned error.

[HortumNecmi]

Thanks for the answer, I connected all bits (used and unused) to a logical operator (or) and assigned the output to one pin. And the problem was solved.

[AqidAyman_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.