arria 10 lvds serdes

[LLCC]

hello,

I was originally using the quartus 17.1 Standard Edition to complete some designs that include LVDS SERDES IPs, and the projects were able to pass compilation successfully. However, when I migrated these projects to 22.1 Pro, compilation errors occurred, even though I am certain that the designs are identical to the original versions.

Here are one of the details of the error messages encountered：

Error(129015): Output port RXDATA on atom "data_rx_top_u0|one_rx_module_u3|lvds_rx_u0|chan17_u0|lvds_0|core|arch_inst|channels[9].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive, is not legally connected and/or configured
Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected
Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected
Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected
Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected
Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected
Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected
Info(11951): Module instance "data_rx_top_u0|one_rx_module_u3|lvds_rx_u0|chan17_u0|lvds_0|core|arch_inst|channels[9].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 6 connected to TXDATA port.

"I am very sure that the code is correct, and it compiled and passed simulation successfully in the 17.1 Standard Edition. Why am I encountering compilation errors in 22.1 Pro?"

[LLCC]

hello,How can I send my project to you privately? Please help me review it to see where the errors are. I really can't find the problem. Thank you.

[HortumNecmi]

Hello, I am having a similar problem, did you solve the problem? 

[AqidAyman_Intel]

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[AqidAyman_Intel]

Hello,

Can you try to regenerate the Altera LVDS SERDES Receiver IP?

Or else, you can try to connect them up in your design.

[LLCC]

Thank you. I have already solved this problem. My feeling is that when the data output by this IP is being processed logically, it requires data from all channels to be used together. For example, if I only use the output data from a single channel to complete a certain logical process, while the output data from other channels is used for another logical process, it may trigger the aforementioned error.

[HortumNecmi]

Thanks for the answer, I connected all bits (used and unused) to a logical operator (or) and assigned the output to one pin. And the problem was solved.

[AqidAyman_Intel]

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[anonimcs]

Hi @HortumNecmi @LLCC ,

I'm facing the same issue, but I already have the bits connected to an input port on one end and to an intermediate pin on the other end. I have this piece of code on my toplevel HDL and I'm not sure what is still missing.

-- group the block/polarization data together for the serdes IPs
    adc_if_0x_rx_in <= T1_X_FCLK & T1_R8X_I & T1_R8X_Q & 
                       T1_X_FCLK & T1_R7X_I & T1_R7X_Q & 
                       T1_X_FCLK & T1_R6X_I & T1_R6X_Q & 
                       T1_X_FCLK & T1_R5X_I & T1_R5X_Q & 
                       T1_X_FCLK & T1_R4X_I & T1_R4X_Q & 
                       T1_X_FCLK & T1_R3X_I & T1_R3X_Q & 
                       T1_X_FCLK & T1_R2X_I & T1_R2X_Q & 
                       T1_X_FCLK & T1_R1X_I & T1_R1X_Q;

-- some code in between

-- LVDS SERDES
    adc_if_0x : component lvds_tile
    port map (
        inclock             => FPGA_REFCLK_ADC, -- adc_sample_clk 50 MHz
        pll_areset          => core_reset,
        pll_locked          => adc_if_0x_pll_locked,
        rx_in               => adc_if_0x_rx_in,
        rx_out              => adc_if_0x_data_out,
        rx_coreclock        => adc_if_0x_rx_coreclock, -- 50 MHz (SERDES Factor 7)
        rx_dpa_reset        => adc_if_0x_rx_dpa_reset,
        rx_dpa_locked       => adc_if_0x_rx_dpa_locked,
        rx_bitslip_ctrl     => adc_if_0x_rx_bitslip_ctrl,
        rx_bitslip_reset    => adc_if_0x_rx_bitslip_rst
    );

The lvds_tile component was defined and added to the project. I'm not getting any syntax error. I'm using a 24 channel approach (see the concatenation at line 2) with a serialization factor of 7. But I'm getting errors like the error given below (I get it for all 24 bits of channel[]) when I try to compile on Quartus Pro 21.3. I've verified that the Platform Designer connects 'adc_if_0x_data_out' to an intermediate block as well, so it's not optimized away either.

I'd be appreciated if you could give me a hand here.

Cheers

Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[23].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured
Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected
Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected
Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected
Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected
Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected
Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected
Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected
Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[0].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port.

[FvM]

Hi,
the error message sounds like your intermediate block doesn't provide an actual connection for SERDES rx_out. Can you try to export at least some channels to top level pins for test?

[anonimcs]

Hi,

I have done it, and it seems like the errors I got are related to the connection of 'rx_dpa_locked'. But feels odd because the compiler complains about the rx_out's connection whereas the errors are gone when I make the dpa_locked connection of the exported qsys component open.