hi, allI use arrio 10 with altera mac+phy ip. how ca I fix this conflict ? project.qsf: set_global_assignment -name FAMILY "Arria 10" set_global_assignment -name DEVICE 10AX115U3F45E2SG# Bank GXBL1F set_location_assignment PIN_AG42 -to tx_serial_data_p set_location_assignment PIN_AF44 -to tx_serial_data_p# Bank GXBL1F set_location_assignment PIN_AG38 -to rx_serial_data_p set_location_assignment PIN_AF40 -to rx_serial_data_p
i get error log: Info (11684): Differential I/O pin "tx_serial_data_p" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "tx_serial_data_p(n)" Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details Critical Warning (12677): No exact pin location assignment(s) for 103 pins of 108 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. Error (14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 HSSI_PMA_TX_BUF(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (175001): The Fitter cannot place 1 HSSI_PMA_TX_BUF, which is within Arria 10 Transceiver Native PHY low_latency_baser_altera_xcvr_native_a10_161_gvv75qa. Info (14596): Information about the failing component(s): Info (175028): The HSSI_PMA_TX_BUF name(s): hft_ethernet_multichan:u_hft_ethernet_multichan|altera_eth_10g_mac_base_r_low_latency_wrap:packet_div_channels.i_u_altera_eth_10g_mac_base_r_low_latency_wrap|low_latency_baser:baser_inst|low_latency_baser_altera_xcvr_native_a10_161_gvv75qa:xcvr_native_a10_0|twentynm_xcvr_native:g_xcvr_native_insts.twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pma_rev_20nm5:inst_twentynm_pma|gen_twentynm_hssi_pma_tx_buf.inst_twentynm_hssi_pma_tx_buf Error (16234): No legal location could be found out of 96 considered location(s). Reasons why each location could not be used are summarized below: Error (175006): Could not find path between the HSSI_PMA_TX_BUF and destination HSSI_RX_PCS_PMA_INTERFACE Info (175027): Destination: HSSI_RX_PCS_PMA_INTERFACE hft_ethernet_multichan:u_hft_ethernet_multichan|altera_eth_10g_mac_base_r_low_latency_wrap:packet_div_channels.i_u_altera_eth_10g_mac_base_r_low_latency_wrap|low_latency_baser:baser_inst|low_latency_baser_altera_xcvr_native_a10_161_gvv75qa:xcvr_native_a10_0|twentynm_xcvr_native:g_xcvr_native_insts.twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface Error (175022): The HSSI_PMA_TX_BUF could not be placed in any location to satisfy its connectivity requirements Info (175021): The HSSI_RX_PCS_PMA_INTERFACE was placed in location HSSIRXPCSPMAINTERFACE_1F1 Info (175029): 94 locations affected Info (175029): HSSIPMATXBUF_1C0 Info (175029): HSSIPMATXBUF_1C1 Info (175029): HSSIPMATXBUF_1C2 Info (175029): HSSIPMATXBUF_1C3 Info (175029): HSSIPMATXBUF_1C4 Info (175029): HSSIPMATXBUF_1C5 Info (175029): HSSIPMATXBUF_1D0 Info (175029): HSSIPMATXBUF_1D1 Info (175029): HSSIPMATXBUF_1D2 Info (175029): HSSIPMATXBUF_1D3 Info (175029): HSSIPMATXBUF_1D4 Info (175029): HSSIPMATXBUF_1D5 Info (175029): and 82 more locations not displayed Error (175003): The HSSI_PMA_TX_BUF location is occupied (2 locations affected) Info (175029): HSSIPMATXBUF_1F0. Already placed at this location: HSSI_PMA_TX_BUF tx_serial_data_p~output_PMA_TX_BUF_FITTER_INSERTED Info (175029): HSSIPMATXBUF_1F1. Already placed at this location: HSSI_PMA_TX_BUF tx_serial_data_p~output_PMA_TX_BUF_FITTER_INSERTED
16.1.2 Build 203 01/18/2017 SJ Pro EditionThe Pin Planner indicates a correct pair. but the Fitter does NOT recognize what Pin Planner is set. Configuration now is a mess when I start deleting XXX(n) nodes that Fitter created, as it will delete both pairs. I am creating the Quartus project from scratch after that, unfortunately. Hoping this will fix.