bidirectional buffer implementation

[Altera_Forum]

Hi, 

How to implement the bidirectional buffer without direction control in FPGA ?.   Regards IHG

[Altera_Forum]

It's not feasible.

[Altera_Forum]

Unless the direction control comes from an external controller. But then the FPGA is a slave

[Altera_Forum]

i'm not too sure what is meant by "direction control", but what i know is you can implement bidirectional buffers that can drive a line HIGH/LOW, or release the line (i.e. drive the line to tri-state) for a read to take place, and you don't need to specify at which time the pin becomes an input or an input. 

 In VHDL at least (probably applies to other HDLs too), you can use an inout and drive the pin at any clock cycle, but of course before you read from the inout pin, you must first release the line (or tri-state the pin), by assigning the pin to 'Z'. Then, at the next clock cycle, you can read the value from the pin (the pin should be now driven from an external device).  Another way is to use "buffer" in VHDL. Here, you can both read and write to the same pin within the same clock cycle. This is useful when you need a feedback path of the pin back into the FPGA.  Hope this helps.

[Altera_Forum]

a "buffer" in VHDL isnt really anything more than a register, not a bidirectional IO pin. 

 And without a direction control, you dont know when to drive the output bus to 'Z'

[Altera_Forum]

--- Quote Start ---  a "buffer" in VHDL isnt really anything more than a register, not a bidirectional IO pin.  --- Quote End ---    You can specify a pin as either in, out, inout, or buffer. Both inout and buffer are bidirectionals, but buffer offers the option of writing and reading to the same pin at the same time.  Buffers (in the sense of amplifiers/drivers) is usually automatically generated by the synthesis tool, and I'm not sure if VHDL has an explicit way of specifying a buffer. What I'd do to create buffers within my logic is just assigning signals, simply like this (below is just an example of connecting 2 buffers together - sorry, i did not test this out, but this should work):  signal s:std_logic_vector(1 downto 0):=(others=>'Z'); attribute keep of s:signal is true; -- this is so that synthesis tools don't optimize away buffers. s(1)<=s(0);

[Altera_Forum]

--- Quote Start ---  You can specify a pin as either in, out, inout, or buffer. Both inout and buffer are bidirectionals, but buffer offers the option of writing and reading to the same pin at the same time.  --- Quote End ---    Sounds like a basic misunderstanding of VHDL features. An interface object of mode buffer is not bidirectional. It's an output, that can be read back internally. By reading a buffer, you only get the internal driving signal state.

[Altera_Forum]

--- Quote Start ---  By reading a buffer, you only get the internal driving signal state.  --- Quote End ---   Thanks for pointing this out. FvM brings up an interesting point. I always thought it was the output that was being "fed-back" and read before it goes out to the pin. But anyway, you're probably right that it's the input to the buffer that gets read.  I guess I'll have to agree that a "buffer" is actually an output (that provides some feedback feature), and cannot be used as a bidirectional pin. I forgot the fact that you can't use a "buffer" to read an external signal driven by another device - this means it synthesizes to only 1 output buffer instead of 2 buffers going in and out for bidirs. You can only use it to read back what you've sent out. So again... thanks FvM for strobing my memory after being stuck in idle for too long.