buffer for clock signal?

[Altera_Forum]

Do Quartus has an buffer for split the clock signal (200MHz)? 

   ----------------------------- clock (200MHz)  | | |  | | |  | | | node1 node2 node3

[Altera_Forum]

--- Quote Start ---  Do Quartus has an buffer for split the clock signal (200MHz)?     ----------------------------- clock (200MHz)  | | |  | | |  | | | node1 node2 node3  --- Quote End ---    Hi,  in case your are using a global input, the clock is distributed to all parts the FPGA.  Kind regards  GPK

[Altera_Forum]

Hi! 

no, the 200 MHz clock is the out of pll, it is internally of fpga.     ------200MHz------ AND PORT------------ . ..............................................| | . ..............................................| | . ..............................................| | . ............................................nodes

[Altera_Forum]

--- Quote Start ---  Hi! no, the 200 MHz clock is the out of pll, it is internally of fpga.     ------200MHz------ AND PORT------------ . ..............................................| | . ..............................................| | . ..............................................| | . ............................................nodes  --- Quote End ---     Hi, why do you want to place a buffer at that point ?   Kind regards  GPK

[Altera_Forum]

because the quartus do: 

what is "ripple clock"?   Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew  Info: Detected ripple clock "inst5" as buffer  Info: Detected ripple clock "myflipflop:inst14|Q" as buffer  Info: Detected gated clock "inst18" as buffer

[Altera_Forum]

--- Quote Start ---  because the quartus do: what is "ripple clock"?   Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew  Info: Detected ripple clock "inst5" as buffer  Info: Detected ripple clock "myflipflop:inst14|Q" as buffer  Info: Detected gated clock "inst18" as buffer  --- Quote End ---    Hi,  I think the Info is a little bit misleading. It only means that Quartus found 3 nodes which drives the clock inputs of e.g. registers. You don't need to do any buffering here, but this kind of clock generation could cause a lot of timing violations.  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Hi,  I think the Info is a little bit misleading. It only means that Quartus found 3 nodes which drives the clock inputs of e.g. registers. You don't need to do any buffering here, but this kind of clock generation could cause a lot of timing violations.  Kind regards  GPK  --- Quote End ---    Hi,  You should find a lot of info's under:  http://www.alteraforum.com/forum/showthread.php?t=2250.  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Hi,  You should find a lot of info's under:  http://www.alteraforum.com/forum/showthread.php?t=2250.  Kind regards  GPK  --- Quote End ---    Hi,  I found an other thread for you:  http://www.alteraforum.com/forum/showthread.php?t=2388.  Kind regards  GPK

[Altera_Forum]

ok! tnx! very good doc!

[Altera_Forum]

from doc: 

"The preferred method of creating enabled clocks is to use the ALTCLKCTRL MegaFunction."   has quartusII(web ed) this megafunction? regards 

[Altera_Forum]

--- Quote Start ---  from doc: "The preferred method of creating enabled clocks is to use the ALTCLKCTRL MegaFunction."   has quartusII(web ed) this megafunction? regards   --- Quote End ---    Hi,  yes. Start the megawizard ( tools -> Megawizard Plug-in manager -> next -> I/O -> ALTCLKCTRL)  Kind regards  GPK

[Altera_Forum]

very good. tnx