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Hi all,

5CGXFC7D6F31C7N is used to implement a TDC in my design with QII14.0. according to timequest analysis results, the average carry delays of adder in a ALM are 52ps, 46ps, 27ps, 26ps respectively for timing corner slow_1100mV_0c, slow_1100mV_85C, fast_1100mV_0c and fast_1100mV_85C. however, real test shows that the average carry delay is only 11ps under room temperature (core voltage is 1118mV under test), and 11ps is not in the range of delay of four timing corners. it seems timequest gives incorrect results. could anyone explain this delay difference between real test and timequest? why the delay value differs so much between real test and timequest result? Regards, ingdxdyLink Copied

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How are you measuring this delay on an internal FPGA path?

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I strongly suspect your measurement is wrong.

The main concern in the design of TDC on fpga is that your signal input will be asynchronous and can't be sampled on registers without timing violation. It also can't be synchronised through two stage registers as this will defeat the purpose. So I don't see how TDC can sort out this issue.- Mark as New
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The timing model needs to account for worst case variation from the fab in each corner + design margin, have you tried sweeping the entire FPGA to see how much variation you get? It's possible you have a faster part or used a faster region on the FPGA.

Also, did you take into account clock skew in your measurement?- Mark as New
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Thanks much for your reply, Jerry, and sorry for my delayed response.

As you said, there are two dedicated adders in a ALM, and according to TQ result, the second adder delay is 0ps, while the first adder contributes the main component of TDL. the granularity of delay element is not as uniform as in CIV, but this is not problem. i have seen other peoples works where they implement TDCs in 28nm(or 20nm?) Xilinx FPGAs, the delay elements there are either non-uniform and there exist many zero-wide bins. Generally, TDCs implemented in more advanced process FPGAs (28nm and below) need bin realignment, for IC delays including clock skews play a more important role than before to decide bins positions. the tuition of bins are arranged according to their physical locations should be adjusted. However, the purpose of my posting this thread is not to discuss how to implement TDCs in CycloneV, but the real test delay value is different from TQ result which makes me puzzled. B&W, ingdxdy- Mark as New
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hi there，

i noticed the same phenomenon and got the same question, did you get the answer for it?

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