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Hi
I have a question : is it possible to connect an enhanced pll input to the fast pll output on the stratix II device? Another question : is it possible to connect one fast pll to another one, on the opposite side of the chip (suppose pll1 to the pll3)? thanksLink Copied
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I thought PLL cascading was allowed for only certain PLL combinations, but I didn't find that with a quick check of PLL cascading references in the device handbook.
To answer questions like these, I typically create a simple test case to try it in Quartus with something that compiles fast.
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