Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs have moved to the Altera Community. Existing Intel Community members can sign in with their current credentials.
21618 Discussions

checks for synthesis rules

Altera_Forum
Honored Contributor II
‎01-24-2012 02:14 PM
1,619 Views

Hi all 

 

I just want to know that apart from DRC checks is there anyother rule checking tool that i can use in synthesis. 

 

I know about design assistant reliability check having 33 set of rules, so is there anyother such check having a rule set?
0 Kudos

Link Copied

2 Replies
Altera_Forum
Honored Contributor II
‎01-27-2012 01:44 PM
721 Views

Are you looking for a more in depth lint checker? If so you might have to do so through whatever simulation tool you use. I know that ActiveHDL has a good linter. I'm not sure if modelsim supports linting.  

 

/Boris
0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎01-28-2012 04:37 AM
721 Views

ohhh ok thanks lethenstrom ..

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.