choice of Transceiver-FPGA Fabric Interface clock rate for 14.1Gbps data rate

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

choice of Transceiver-FPGA Fabric Interface clock rate for 14.1Gbps data rate

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Hi,

I have a question regarding the maximum clock frequency applicable to Transceiver-FPGA Fabric Interface in Stratix-V device. based on switching charactristic information (Table 2–19. in Stratix-V devie handbook) the Transceiver-FPGA Fabric Interface speed should be no more than 283 MHz for –1 speed grade. this corresponds to a 50bit Transceiver-FPGA Fabric interface width.

is it possible to use a 40bit width interface with clock rate of around 350MHz. and if so, what is the recommended core clock in a FPGA about half resource populated.

thanks,

bahman

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