Ok, consider generating clk-enable instead of clk. I mean apply 50MHz to all design but when you want 8KHz apply its enable and when you want 256KHz apply the other enable.
if this good for your design then:
to generate clk-enable at 8KHz from 50MHz you need to divide your clock by
50,000/8 = 6250 (integer result)
to generate clk-enable at 256KHz from 50MHz you need to divide your clock by 50,000/256 = 195.3125 (non-integer).
This non-integer gets nasty but don't worry. If you can change source clk frequency you may get rid of this problem easily, otherwise you can do amodulo adder(for both cases) as follows:
for 8KHz:
get a counter that runs freely and continuously from 0 to 6249 on your 50MHz clock adding 1 each time.
if count = 6249 then
count <= 0;
en1 <= '1';
else
count <= count + 1;
en1 <= '0';
end if;
so this easy,just a counter, you can call 1 modulo 6250
for 256KHz:
get another counter that counts from 0 to (50000+256) adding 256 each time.
if count2 >= 50000 then
count2 <= count2 +256 -50000; -- wrap up
en2 <= '1';
else
count2 <= count2 + 256;
en2 <= '0';
end if;
this is a bit more difficult, it is 256 modulo 50000
You will need to complete and test the code, I haven't debugged it(straight from my head)
