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Honored Contributor I
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clock mux with internally generated inputs

I generated a clock mux using altclkctrl megawizard. My input signals, both the clocks and select signal are generated internally. They are not coming from the clock pin or PLL. The quartus tool complains that the inputs should come from either the clock pin or PLL. How to work around this issue? I am porting my xilinx FPGA design to altera. In xilinx, I used BUFGMUX to do this.

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Honored Contributor I
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Annoyingly, the altclkctrl can only be driven by a PLL for dynamic switching. If the signals are coming internally, then building a mux out of logic shouldn't really matter from a timing perspective. The only thing missing is a glitch-free switchover(which can be built with logic, it's just not as trivial as a 2:1 mux). Are you dynamically switching clocks, or choosing one and sticking with it?

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Honored Contributor I
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Thanks for your reply. I am dynamically switching clocks. Do you have an example verilog code for glitch free clock mux? Also, do I need to take care of any special timing issues? I am doing an ASIC prototyping and I have to use 8 of these muxes in different places.

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Honored Contributor I
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Sorry, but no. I think Altera has one somewhere but not sure. I'm sure there are some on the web somewhere. Might be a good post(maybe a new thread?). Is it a 2:1 mux or larger? The key is to disable one clock(by grounding the output after a falling edge) before enabling the other clock(release it's grouned output after a falling edge). But I just don't have a good piece of code.

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Honored Contributor I
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 Originally Posted by Rysc 

Sorry, but no. I think Altera has one somewhere but not sure. I'm sure there are some on the web somewhere. Might be a good post(maybe a new thread?). Is it a 2:1 mux or larger? The key is to disable one clock(by grounding the output after a falling edge) before enabling the other clock(release it's grouned output after a falling edge). But I just don't have a good piece of code.

Hi,

 

have a look to the attached document. I was posted by Kwalt in the year 2008.

It is more related to timing analysis, but gives also some hints for clock multiplexing.

 

Kind regards

 

GPK

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