clock select for internal FPGA logic

Altera_Forum · ‎10-13-2015

HI

I am working on Arria v FPGA and I am writing the code for transferring serial data to a remote module using RS-422 protocol. Here I need to dynamically change the clock rate depending on some parameters. I am planning to use the clk select megafunction in ALTCLKCTRL core. I would be generating all of the clocks and i would mux the required clk. Can I use this design for tapping the clock and using it in my custom FPGA logic.

Altera_Forum · ‎10-13-2015

You question wasn't clear on what you need to change. If you need to change the RS422 baud rate but leave the rest of the logic running normlly use a UART with a programmable baud rate. QSYS comes with "Altera 16550 Compatible UART". It has multiplier and divisor registers for the clock rate. If you choose the clock wisely, you can probably set the desired rates.

I don't think you can use a multiplexer, or any other logic on clock signals. I've been told that anyway.

Altera_Forum · ‎10-14-2015

HI Galfonz,

Thanks for the reply.

I may need to write my custom transmitter and receiver as I am not following any UART protocol. The electrical characteristics of the line are just following the RS-422 specifications. Initially Tx and Rx rate will be defaluted to low baud rate and soon as I receive register configuration (from another remote module) for a higher clock rate I may need to switch to higher clock rate. So for this implemetation I would be deriving a refrence clock(125 MHz) from PLL and derive all the required clocks using clock dividers (62.5 MHz, 31.25 etc ...). I would input all these clocks to clock select core of ALTCLKCTRL and select the desired clock depending on register conf. My question would be is it possible to input the divided clocks to the ALTCLKCTRL core and can I use the clock output from core to drive my internal logic?

Altera_Forum · ‎10-14-2015

Not using available UART modules is certainly the hard way to do it. You should look at the PLL re-configuration feature. It would be more flexible and probably use less resources than what you've outlined.

Altera_Forum · ‎10-15-2015

Thanks for the suggestion of using PLL reconfiguration feature